Jump to content

ILI9325 with STM32437I-EVAL


davidelbaze

Recommended Posts

Hi all,

I have some trouble those days to get my LCD working with uGFX.

Here are my files :

main.c


#include "ch.h"
#include "hal.h"
#include "gfx.h"

int main(void) {

coord_t width, height;
font_t font1, font2, font3, font4;
const char *msg;
uint32_t lcdid = 0;


gfxInit();

gdispClear(Green);
font1 = gdispOpenFont("UI2");

gdispDrawString(10, 10, "Writing with Font 'UI2'", font1, Green);



palSetPadMode(GPIOC, GPIOC_LED4, PAL_MODE_OUTPUT_PUSHPULL);

while(TRUE) {
gfxSleepMilliseconds(500);

palSetPad(GPIOC, GPIOC_LED4); /* Blue LED */
chThdSleepMilliseconds(1400);
palClearPad(GPIOC, GPIOC_LED4);
chThdSleepMilliseconds(200);
}
}

gdisp_lld_board.h



#ifndef GDISP_LLD_BOARD_H
#define GDISP_LLD_BOARD_H

#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x08000000)) /* RS = 1 */

#define GDISP_USE_FSMC


static inline void gdisp_lld_init_board(void) {

rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);

/* set pin modes */
IOBus busD = {GPIOD, PAL_WHOLE_PORT, 0};
IOBus busE = {GPIOE, PAL_WHOLE_PORT, 0};

palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));


/* FSMC timing register configuration */
uint32_t FSMC_Bank = 0;
/* FSMC timing register configuration */
FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
| (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
| FSMC_BTR1_BUSTURN_0;

/* Bank1 NOR/PSRAM control register configuration
* Write enable, memory databus width set to 16 bit, memory bank enable */
FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_WREN | FSMC_BCR1_MWID_0 | FSMC_BCR1_MBKEN;
FSMC_Bank1->BTCR[((uint32_t)0x00000004)] |= ((uint32_t)0x00000001);


/* Color LCD configuration*/
FSMC_Bank1->BTCR[((uint32_t)0x00000004)] =
(((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000010) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00001000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000) | ((uint32_t)0x00000000));

/* FSMC_Bank1_NORSRAM4 configuration */
FSMC_Bank1->BTCR[((uint32_t)0x00000004)+1] = (5 | (0 << 4) | (9 << 8) | (0 << 16) | (0 << 20) | (0 << 24) | ((uint32_t)0x00000000));

///Enable Bank 3/
FSMC_Bank1->BTCR[((uint32_t)0x00000004)] |= ((uint32_t)0x00000001);
FSMC_Bank1E->BWTR[((uint32_t)0x00000004)] = 0x0FFFFFFF;



}

static inline void gdisp_lld_reset_pin(bool_t state) {
/*if(state)
palClearPad(GPIOE, GPIOE_TFT_RST);
else
palSetPad(GPIOE, GPIOE_TFT_RST);*/
(void) state;
}

static inline void acquire_bus(void) {
/* Nothing to do here since LCD is the only device on that bus */
}

static inline void release_bus(void) {
/* Nothing to do here since LCD is the only device on that bus */
}

static inline void gdisp_lld_write_index(uint16_t reg) {
GDISP_REG = reg;
}

static inline void gdisp_lld_write_data(uint16_t data) {
GDISP_RAM = data;
}

static inline uint16_t gdisp_lld_read_data(void) {
return GDISP_RAM;
}

static inline void gdisp_lld_backlight(uint8_t percent) {
/*if(percent == 100)
palClearPad(GPIOD, GPIOD_TFT_LIGHT);
else
palSetPad(GPIOD, GPIOD_TFT_LIGHT);*/
}

#endif

Link to comment
Share on other sites

and the board.h

board.h
[code]
#ifndef _BOARD_H_
#define _BOARD_H_

#define BOARD_ST_STM32437I_EVAL
#define BOARD_NAME "St STM32437I_EVAL"



#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0
#endif

#if !defined(STM32_HSECLK)
#define STM32_HSECLK 25000000
#endif


#define STM32_VDD 330


#define STM32F4XX


#define GPIOD_FSMC_D2 0
#define GPIOD_FSMC_D3 1
#define GPIOD_PIN2 2
#define GPIOD_PIN3 3
#define GPIOD_FSMC_NOE 4
#define GPIOD_FSMC_NWE 5
#define GPIOD_PIN6 6
#define GPIOD_FSMC_NE1 7
#define GPIOD_FSMC_D13 8
#define GPIOD_FSMC_D14 9
#define GPIOD_FSMC_D15 10
#define GPIOD_FSMC_A16 11
#define GPIOD_FSMC_A17 12
#define GPIOD_FSMC_A18 13
#define GPIOD_FSMC_D0 14
#define GPIOD_FSMC_D1 15

#define GPIOE_FSMC_NBL0 0
#define GPIOE_FSMC_NBL1 1
#define GPIOE_FSMC_A23 2
#define GPIOE_FSMC_A19 3
#define GPIOE_FSMC_A20 4
#define GPIOE_FSMC_A21 5
#define GPIOE_FSMC_A22 6
#define GPIOE_FSMC_D4 7
#define GPIOE_FSMC_D5 8
#define GPIOE_FSMC_D6 9
#define GPIOE_FSMC_D7 10
#define GPIOE_FSMC_D8 11
#define GPIOE_FSMC_D9 12
#define GPIOE_FSMC_D10 13
#define GPIOE_FSMC_D11 14
#define GPIOE_FSMC_D12 15

#define GPIOF_FSMC_A0 0
#define GPIOF_FSMC_A1 1
#define GPIOF_FSMC_A2 2
#define GPIOF_FSMC_A3 3
#define GPIOF_FSMC_A4 4
#define GPIOF_FSMC_A5 5
#define GPIOF_PIN6 6
#define GPIOF_PIN7 7
#define GPIOF_PIN8 8
#define GPIOF_PIN9 9
#define GPIOF_PIN10 10
#define GPIOF_USB_FS_FAULT_OVER_CURRENT 11
#define GPIOF_FSMC_A6 12
#define GPIOF_FSMC_A7 13
#define GPIOF_FSMC_A8 14
#define GPIOF_FSMC_A9 15

#define GPIOG_FSMC_A10 0
#define GPIOG_FSMC_A11 1
#define GPIOG_FSMC_A12 2
#define GPIOG_FSMC_A13 3
#define GPIOG_FSMC_A14 4
#define GPIOG_FSMC_A15 5
#define GPIOG_LED1 6
#define GPIOG_PIN7 7
#define GPIOG_LED2 8
#define GPIOG_FSMC_NE2 9
#define GPIOG_PIN10 10
#define GPIOG_ETH_RMII_TXEN 11
#define GPIOG_PIN12 12
#define GPIOG_ETH_RMII_TXD0 13
#define GPIOG_ETH_RMII_TXD1 14
#define GPIOG_BUTTON_USER 15

#define GPIOH_PIN0 0
#define GPIOH_PIN1 1
#define GPIOH_PIN2 2
#define GPIOH_PIN3 3
#define GPIOH_OTG_HS_ULPI_NXT 4
#define GPIOH_OTG_FS_PowerSwitchON 5
#define GPIOH_PIN6 6
#define GPIOH_PIN7 7
#define GPIOH_PIN8 8
#define GPIOH_PIN9 9
#define GPIOH_PIN10 10
#define GPIOH_PIN11 11
#define GPIOH_PIN12 12
#define GPIOH_SD_Detect 13
#define GPIOH_PIN14 14
#define GPIOH_PIN15 15

#define GPIOI_PIN0 0
#define GPIOI_PIN1 1
#define GPIOI_PIN2 2
#define GPIOI_PIN3 3
#define GPIOI_PIN4 4
#define GPIOI_PIN5 5
#define GPIOI_PIN6 6
#define GPIOI_PIN7 7
#define GPIOI_PIN8 8
#define GPIOI_LED3 9
#define GPIOI_PIN10 10
#define GPIOI_OTG_HS_ULPI_DIR 11
#define GPIOI_PIN12 12
#define GPIOI_PIN13 13
#define GPIOI_PIN14 14
#define GPIOI_PIN15 15


#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))


#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FSMC_D2) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D3) | \
PIN_MODE_ALTERNATE(GPIOD_PIN2) | \
PIN_MODE_INPUT(GPIOD_PIN3) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_NOE) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_NWE) | \
PIN_MODE_INPUT(GPIOD_PIN6) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_NE1) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D13) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D14) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D15) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_A16) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_A17) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_A18) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D0) | \
PIN_MODE_ALTERNATE(GPIOD_FSMC_D1))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D2) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D3) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_NOE) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_NWE) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_NE1) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D13) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D14) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D15) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_A16) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_A17) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_A18) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D0) | \
PIN_OTYPE_PUSHPULL(GPIOD_FSMC_D1))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_FSMC_D2) | \
PIN_OSPEED_100M(GPIOD_FSMC_D3) | \
PIN_OSPEED_100M(GPIOD_PIN2) | \
PIN_OSPEED_100M(GPIOD_PIN3) | \
PIN_OSPEED_100M(GPIOD_FSMC_NOE) | \
PIN_OSPEED_100M(GPIOD_FSMC_NWE) | \
PIN_OSPEED_100M(GPIOD_PIN6) | \
PIN_OSPEED_100M(GPIOD_FSMC_NE1) | \
PIN_OSPEED_100M(GPIOD_FSMC_D13) | \
PIN_OSPEED_100M(GPIOD_FSMC_D14) | \
PIN_OSPEED_100M(GPIOD_FSMC_D15) | \
PIN_OSPEED_100M(GPIOD_FSMC_A16) | \
PIN_OSPEED_100M(GPIOD_FSMC_A17) | \
PIN_OSPEED_100M(GPIOD_FSMC_A18) | \
PIN_OSPEED_100M(GPIOD_FSMC_D0) | \
PIN_OSPEED_100M(GPIOD_FSMC_D1))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FSMC_D2) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D3) | \
PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_NOE) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_NWE) | \
PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_NE1) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D13) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D14) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D15) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_A16) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_A17) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_A18) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D0) | \
PIN_PUPDR_FLOATING(GPIOD_FSMC_D1))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FSMC_D2) | \
PIN_ODR_HIGH(GPIOD_FSMC_D3) | \
PIN_ODR_HIGH(GPIOD_PIN2) | \
PIN_ODR_HIGH(GPIOD_PIN3) | \
PIN_ODR_HIGH(GPIOD_FSMC_NOE) | \
PIN_ODR_HIGH(GPIOD_FSMC_NWE) | \
PIN_ODR_HIGH(GPIOD_PIN6) | \
PIN_ODR_HIGH(GPIOD_FSMC_NE1) | \
PIN_ODR_HIGH(GPIOD_FSMC_D13) | \
PIN_ODR_HIGH(GPIOD_FSMC_D14) | \
PIN_ODR_HIGH(GPIOD_FSMC_D15) | \
PIN_ODR_HIGH(GPIOD_FSMC_A16) | \
PIN_ODR_HIGH(GPIOD_FSMC_A17) | \
PIN_ODR_HIGH(GPIOD_FSMC_A18) | \
PIN_ODR_HIGH(GPIOD_FSMC_D0) | \
PIN_ODR_HIGH(GPIOD_FSMC_D1))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FSMC_D2, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_D3, 12) | \
PIN_AFIO_AF(GPIOD_PIN2, 12) | \
PIN_AFIO_AF(GPIOD_PIN3, 0) | \
PIN_AFIO_AF(GPIOD_FSMC_NOE, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_NWE, 12) | \
PIN_AFIO_AF(GPIOD_PIN6, 0) | \
PIN_AFIO_AF(GPIOD_FSMC_NE1, 12))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FSMC_D13, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_D14, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_D15, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_A16, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_A17, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_A18, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_D0, 12) | \
PIN_AFIO_AF(GPIOD_FSMC_D1, 12))

#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FSMC_NBL0) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_NBL1) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_A23) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_A19) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_A20) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_A21) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_A22) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D4) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D5) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D6) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D7) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D8) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D9) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D10) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D11) | \
PIN_MODE_ALTERNATE(GPIOE_FSMC_D12))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FSMC_NBL0) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_NBL1) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_A23) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_A19) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_A20) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_A21) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_A22) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D4) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D5) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D6) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D7) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D8) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D9) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D10) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D11) | \
PIN_OTYPE_PUSHPULL(GPIOE_FSMC_D12))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_FSMC_NBL0) | \
PIN_OSPEED_100M(GPIOE_FSMC_NBL1) | \
PIN_OSPEED_100M(GPIOE_FSMC_A23) | \
PIN_OSPEED_100M(GPIOE_FSMC_A19) | \
PIN_OSPEED_100M(GPIOE_FSMC_A20) | \
PIN_OSPEED_100M(GPIOE_FSMC_A21) | \
PIN_OSPEED_100M(GPIOE_FSMC_A22) | \
PIN_OSPEED_100M(GPIOE_FSMC_D4) | \
PIN_OSPEED_100M(GPIOE_FSMC_D5) | \
PIN_OSPEED_100M(GPIOE_FSMC_D6) | \
PIN_OSPEED_100M(GPIOE_FSMC_D7) | \
PIN_OSPEED_100M(GPIOE_FSMC_D8) | \
PIN_OSPEED_100M(GPIOE_FSMC_D9) | \
PIN_OSPEED_100M(GPIOE_FSMC_D10) | \
PIN_OSPEED_100M(GPIOE_FSMC_D11) | \
PIN_OSPEED_100M(GPIOE_FSMC_D12))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FSMC_NBL0) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_NBL1) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_A23) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_A19) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_A20) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_A21) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_A22) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D4) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D5) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D6) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D7) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D8) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D9) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D10) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D11) | \
PIN_PUPDR_FLOATING(GPIOE_FSMC_D12))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FSMC_NBL0) | \
PIN_ODR_HIGH(GPIOE_FSMC_NBL1) | \
PIN_ODR_HIGH(GPIOE_FSMC_A23) | \
PIN_ODR_HIGH(GPIOE_FSMC_A19) | \
PIN_ODR_HIGH(GPIOE_FSMC_A20) | \
PIN_ODR_HIGH(GPIOE_FSMC_A21) | \
PIN_ODR_HIGH(GPIOE_FSMC_A22) | \
PIN_ODR_HIGH(GPIOE_FSMC_D4) | \
PIN_ODR_HIGH(GPIOE_FSMC_D5) | \
PIN_ODR_HIGH(GPIOE_FSMC_D6) | \
PIN_ODR_HIGH(GPIOE_FSMC_D7) | \
PIN_ODR_HIGH(GPIOE_FSMC_D8) | \
PIN_ODR_HIGH(GPIOE_FSMC_D9) | \
PIN_ODR_HIGH(GPIOE_FSMC_D10) | \
PIN_ODR_HIGH(GPIOE_FSMC_D11) | \
PIN_ODR_HIGH(GPIOE_FSMC_D12))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FSMC_NBL0, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_NBL1, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_A23, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_A19, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_A20, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_A21, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_A22, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D4, 12))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FSMC_D5, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D6, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D7, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D8, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D9, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D10, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D11, 12) | \
PIN_AFIO_AF(GPIOE_FSMC_D12, 12))

#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FSMC_A0) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A1) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A2) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A3) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A4) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A5) | \
PIN_MODE_INPUT(GPIOF_PIN6) | \
PIN_MODE_INPUT(GPIOF_PIN7) | \
PIN_MODE_INPUT(GPIOF_PIN8) | \
PIN_MODE_INPUT(GPIOF_PIN9) | \
PIN_MODE_INPUT(GPIOF_PIN10) | \
PIN_MODE_INPUT(GPIOF_USB_FS_FAULT_OVER_CURRENT) |\
PIN_MODE_ALTERNATE(GPIOF_FSMC_A6) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A7) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A8) | \
PIN_MODE_ALTERNATE(GPIOF_FSMC_A9))
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A0) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A1) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A2) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A3) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A4) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A5) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT_OVER_CURRENT) |\
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A6) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A7) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A8) | \
PIN_OTYPE_PUSHPULL(GPIOF_FSMC_A9))
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_FSMC_A0) | \
PIN_OSPEED_100M(GPIOF_FSMC_A1) | \
PIN_OSPEED_100M(GPIOF_FSMC_A2) | \
PIN_OSPEED_100M(GPIOF_FSMC_A3) | \
PIN_OSPEED_100M(GPIOF_FSMC_A4) | \
PIN_OSPEED_100M(GPIOF_FSMC_A5) | \
PIN_OSPEED_100M(GPIOF_PIN6) | \
PIN_OSPEED_100M(GPIOF_PIN7) | \
PIN_OSPEED_100M(GPIOF_PIN8) | \
PIN_OSPEED_100M(GPIOF_PIN9) | \
PIN_OSPEED_100M(GPIOF_PIN10) | \
PIN_OSPEED_100M(GPIOF_USB_FS_FAULT_OVER_CURRENT) |\
PIN_OSPEED_100M(GPIOF_FSMC_A6) | \
PIN_OSPEED_100M(GPIOF_FSMC_A7) | \
PIN_OSPEED_100M(GPIOF_FSMC_A8) | \
PIN_OSPEED_100M(GPIOF_FSMC_A9))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FSMC_A0) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A1) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A2) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A3) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A4) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A5) | \
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT_OVER_CURRENT) |\
PIN_PUPDR_FLOATING(GPIOF_FSMC_A6) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A7) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A8) | \
PIN_PUPDR_FLOATING(GPIOF_FSMC_A9))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FSMC_A0) | \
PIN_ODR_HIGH(GPIOF_FSMC_A1) | \
PIN_ODR_HIGH(GPIOF_FSMC_A2) | \
PIN_ODR_HIGH(GPIOF_FSMC_A3) | \
PIN_ODR_HIGH(GPIOF_FSMC_A4) | \
PIN_ODR_HIGH(GPIOF_FSMC_A5) | \
PIN_ODR_HIGH(GPIOF_PIN6) | \
PIN_ODR_HIGH(GPIOF_PIN7) | \
PIN_ODR_HIGH(GPIOF_PIN8) | \
PIN_ODR_HIGH(GPIOF_PIN9) | \
PIN_ODR_HIGH(GPIOF_PIN10) | \
PIN_ODR_HIGH(GPIOF_USB_FS_FAULT_OVER_CURRENT) |\
PIN_ODR_HIGH(GPIOF_FSMC_A6) | \
PIN_ODR_HIGH(GPIOF_FSMC_A7) | \
PIN_ODR_HIGH(GPIOF_FSMC_A8) | \
PIN_ODR_HIGH(GPIOF_FSMC_A9))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FSMC_A0, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A1, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A2, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A3, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A4, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A5, 12) | \
PIN_AFIO_AF(GPIOF_PIN6, 0) | \
PIN_AFIO_AF(GPIOF_PIN7, 0))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
PIN_AFIO_AF(GPIOF_PIN9, 0) | \
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
PIN_AFIO_AF(GPIOF_USB_FS_FAULT_OVER_CURRENT, 0) |\
PIN_AFIO_AF(GPIOF_FSMC_A6, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A7, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A8, 12) | \
PIN_AFIO_AF(GPIOF_FSMC_A9, 12))

#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FSMC_A10) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_A11) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_A12) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_A13) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_A14) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_A15) | \
PIN_MODE_OUTPUT(GPIOG_LED1) | \
PIN_MODE_INPUT(GPIOG_PIN7) | \
PIN_MODE_OUTPUT(GPIOG_LED2) | \
PIN_MODE_ALTERNATE(GPIOG_FSMC_NE2) | \
PIN_MODE_OUTPUT(GPIOG_PIN10) | \
PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\
PIN_MODE_INPUT(GPIOG_PIN12) | \
PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\
PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\
PIN_MODE_INPUT(GPIOG_BUTTON_USER))
#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A10) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A11) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A12) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A13) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A14) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_A15) | \
PIN_OTYPE_PUSHPULL(GPIOG_LED1) | \
PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOG_LED2) | \
PIN_OTYPE_PUSHPULL(GPIOG_FSMC_NE2) | \
PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\
PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\
PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\
PIN_OTYPE_PUSHPULL(GPIOG_BUTTON_USER))
#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_FSMC_A10) | \
PIN_OSPEED_100M(GPIOG_FSMC_A11) | \
PIN_OSPEED_100M(GPIOG_FSMC_A12) | \
PIN_OSPEED_100M(GPIOG_FSMC_A13) | \
PIN_OSPEED_100M(GPIOG_FSMC_A14) | \
PIN_OSPEED_100M(GPIOG_FSMC_A15) | \
PIN_OSPEED_100M(GPIOG_LED1) | \
PIN_OSPEED_100M(GPIOG_PIN7) | \
PIN_OSPEED_100M(GPIOG_LED2) | \
PIN_OSPEED_100M(GPIOG_FSMC_NE2) | \
PIN_OSPEED_100M(GPIOG_PIN10) | \
PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \
PIN_OSPEED_100M(GPIOG_PIN12) | \
PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \
PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \
PIN_OSPEED_100M(GPIOG_BUTTON_USER))
#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FSMC_A10) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_A11) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_A12) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_A13) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_A14) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_A15) | \
PIN_PUPDR_PULLUP(GPIOG_LED1) | \
PIN_PUPDR_PULLUP(GPIOG_PIN7) | \
PIN_PUPDR_PULLDOWN(GPIOG_LED2) | \
PIN_PUPDR_FLOATING(GPIOG_FSMC_NE2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\
PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\
PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\
PIN_PUPDR_PULLUP(GPIOG_BUTTON_USER))
#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FSMC_A10) | \
PIN_ODR_HIGH(GPIOG_FSMC_A11) | \
PIN_ODR_HIGH(GPIOG_FSMC_A12) | \
PIN_ODR_HIGH(GPIOG_FSMC_A13) | \
PIN_ODR_HIGH(GPIOG_FSMC_A14) | \
PIN_ODR_HIGH(GPIOG_FSMC_A15) | \
PIN_ODR_LOW(GPIOG_LED1) | \
PIN_ODR_HIGH(GPIOG_PIN7) | \
PIN_ODR_LOW(GPIOG_LED2) | \
PIN_ODR_HIGH(GPIOG_FSMC_NE2) | \
PIN_ODR_HIGH(GPIOG_PIN10) | \
PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \
PIN_ODR_HIGH(GPIOG_PIN12) | \
PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \
PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \
PIN_ODR_HIGH(GPIOG_BUTTON_USER))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FSMC_A10, 12) | \
PIN_AFIO_AF(GPIOG_FSMC_A11, 12) | \
PIN_AFIO_AF(GPIOG_FSMC_A12, 12) | \
PIN_AFIO_AF(GPIOG_FSMC_A13, 12) | \
PIN_AFIO_AF(GPIOG_FSMC_A14, 12) | \
PIN_AFIO_AF(GPIOG_FSMC_A15, 12) | \
PIN_AFIO_AF(GPIOG_LED1, 0) | \
PIN_AFIO_AF(GPIOG_PIN7, 0))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_LED2, 0) | \
PIN_AFIO_AF(GPIOG_FSMC_NE2, 12) | \
PIN_AFIO_AF(GPIOG_PIN10, 0) | \
PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \
PIN_AFIO_AF(GPIOG_PIN12, 0) | \
PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \
PIN_AFIO_AF(GPIOG_BUTTON_USER, 0))

#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | \
PIN_MODE_INPUT(GPIOH_PIN1) | \
PIN_MODE_INPUT(GPIOH_PIN2) | \
PIN_MODE_INPUT(GPIOH_PIN3) | \
PIN_MODE_ALTERNATE(GPIOH_OTG_HS_ULPI_NXT) |\
PIN_MODE_OUTPUT(GPIOH_OTG_FS_PowerSwitchON) |\
PIN_MODE_INPUT(GPIOH_PIN6) | \
PIN_MODE_INPUT(GPIOH_PIN7) | \
PIN_MODE_INPUT(GPIOH_PIN8) | \
PIN_MODE_INPUT(GPIOH_PIN9) | \
PIN_MODE_INPUT(GPIOH_PIN10) | \
PIN_MODE_INPUT(GPIOH_PIN11) | \
PIN_MODE_INPUT(GPIOH_PIN12) | \
PIN_MODE_INPUT(GPIOH_SD_Detect) | \
PIN_MODE_INPUT(GPIOH_PIN14) | \
PIN_MODE_INPUT(GPIOH_PIN15))
#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOH_OTG_HS_ULPI_NXT) |\
PIN_OTYPE_PUSHPULL(GPIOH_OTG_FS_PowerSwitchON) |\
PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOH_SD_Detect) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_PIN0) | \
PIN_OSPEED_100M(GPIOH_PIN1) | \
PIN_OSPEED_100M(GPIOH_PIN2) | \
PIN_OSPEED_100M(GPIOH_PIN3) | \
PIN_OSPEED_100M(GPIOH_OTG_HS_ULPI_NXT) |\
PIN_OSPEED_100M(GPIOH_OTG_FS_PowerSwitchON) |\
PIN_OSPEED_100M(GPIOH_PIN6) | \
PIN_OSPEED_100M(GPIOH_PIN7) | \
PIN_OSPEED_100M(GPIOH_PIN8) | \
PIN_OSPEED_100M(GPIOH_PIN9) | \
PIN_OSPEED_100M(GPIOH_PIN10) | \
PIN_OSPEED_100M(GPIOH_PIN11) | \
PIN_OSPEED_100M(GPIOH_PIN12) | \
PIN_OSPEED_100M(GPIOH_SD_Detect) | \
PIN_OSPEED_100M(GPIOH_PIN14) | \
PIN_OSPEED_100M(GPIOH_PIN15))
#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_PIN0) | \
PIN_PUPDR_FLOATING(GPIOH_PIN1) | \
PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
PIN_PUPDR_FLOATING(GPIOH_OTG_HS_ULPI_NXT) |\
PIN_PUPDR_PULLUP(GPIOH_OTG_FS_PowerSwitchON) |\
PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
PIN_PUPDR_PULLUP(GPIOH_SD_Detect) | \
PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
PIN_PUPDR_PULLUP(GPIOH_PIN15))
#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | \
PIN_ODR_HIGH(GPIOH_PIN1) | \
PIN_ODR_HIGH(GPIOH_PIN2) | \
PIN_ODR_HIGH(GPIOH_PIN3) | \
PIN_ODR_HIGH(GPIOH_OTG_HS_ULPI_NXT) | \
PIN_ODR_HIGH(GPIOH_OTG_FS_PowerSwitchON) |\
PIN_ODR_HIGH(GPIOH_PIN6) | \
PIN_ODR_HIGH(GPIOH_PIN7) | \
PIN_ODR_HIGH(GPIOH_PIN8) | \
PIN_ODR_HIGH(GPIOH_PIN9) | \
PIN_ODR_HIGH(GPIOH_PIN10) | \
PIN_ODR_HIGH(GPIOH_PIN11) | \
PIN_ODR_HIGH(GPIOH_PIN12) | \
PIN_ODR_HIGH(GPIOH_SD_Detect) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | \
PIN_AFIO_AF(GPIOH_PIN1, 0) | \
PIN_AFIO_AF(GPIOH_PIN2, 0) | \
PIN_AFIO_AF(GPIOH_PIN3, 0) | \
PIN_AFIO_AF(GPIOH_OTG_HS_ULPI_NXT, 10) |\
PIN_AFIO_AF(GPIOH_OTG_FS_PowerSwitchON, 0) |\
PIN_AFIO_AF(GPIOH_PIN6, 0) | \
PIN_AFIO_AF(GPIOH_PIN7, 0))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
PIN_AFIO_AF(GPIOH_PIN12, 0) | \
PIN_AFIO_AF(GPIOH_SD_Detect, 0) | \
PIN_AFIO_AF(GPIOH_PIN14, 0) | \
PIN_AFIO_AF(GPIOH_PIN15, 0))

#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
PIN_MODE_INPUT(GPIOI_PIN1) | \
PIN_MODE_INPUT(GPIOI_PIN2) | \
PIN_MODE_INPUT(GPIOI_PIN3) | \
PIN_MODE_INPUT(GPIOI_PIN4) | \
PIN_MODE_INPUT(GPIOI_PIN5) | \
PIN_MODE_INPUT(GPIOI_PIN6) | \
PIN_MODE_INPUT(GPIOI_PIN7) | \
PIN_MODE_INPUT(GPIOI_PIN8) | \
PIN_MODE_OUTPUT(GPIOI_LED3) | \
PIN_MODE_INPUT(GPIOI_PIN10) | \
PIN_MODE_ALTERNATE(GPIOI_OTG_HS_ULPI_DIR) |\
PIN_MODE_INPUT(GPIOI_PIN12) | \
PIN_MODE_INPUT(GPIOI_PIN13) | \
PIN_MODE_INPUT(GPIOI_PIN14) | \
PIN_MODE_INPUT(GPIOI_PIN15))
#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOI_LED3) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOI_OTG_HS_ULPI_DIR) |\
PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
PIN_OSPEED_100M(GPIOI_PIN1) | \
PIN_OSPEED_100M(GPIOI_PIN2) | \
PIN_OSPEED_100M(GPIOI_PIN3) | \
PIN_OSPEED_100M(GPIOI_PIN4) | \
PIN_OSPEED_100M(GPIOI_PIN5) | \
PIN_OSPEED_100M(GPIOI_PIN6) | \
PIN_OSPEED_100M(GPIOI_PIN7) | \
PIN_OSPEED_100M(GPIOI_PIN8) | \
PIN_OSPEED_100M(GPIOI_LED3) | \
PIN_OSPEED_100M(GPIOI_PIN10) | \
PIN_OSPEED_100M(GPIOI_OTG_HS_ULPI_DIR) |\
PIN_OSPEED_100M(GPIOI_PIN12) | \
PIN_OSPEED_100M(GPIOI_PIN13) | \
PIN_OSPEED_100M(GPIOI_PIN14) | \
PIN_OSPEED_100M(GPIOI_PIN15))
#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
PIN_PUPDR_FLOATING(GPIOI_LED3) | \
PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
PIN_PUPDR_FLOATING(GPIOI_OTG_HS_ULPI_DIR) |\
PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
PIN_PUPDR_PULLUP(GPIOI_PIN15))
#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
PIN_ODR_HIGH(GPIOI_PIN1) | \
PIN_ODR_HIGH(GPIOI_PIN2) | \
PIN_ODR_HIGH(GPIOI_PIN3) | \
PIN_ODR_HIGH(GPIOI_PIN4) | \
PIN_ODR_HIGH(GPIOI_PIN5) | \
PIN_ODR_HIGH(GPIOI_PIN6) | \
PIN_ODR_HIGH(GPIOI_PIN7) | \
PIN_ODR_HIGH(GPIOI_PIN8) | \
PIN_ODR_LOW(GPIOI_LED3) | \
PIN_ODR_HIGH(GPIOI_PIN10) | \
PIN_ODR_HIGH(GPIOI_OTG_HS_ULPI_DIR) | \
PIN_ODR_HIGH(GPIOI_PIN12) | \
PIN_ODR_HIGH(GPIOI_PIN13) | \
PIN_ODR_HIGH(GPIOI_PIN14) | \
PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
PIN_AFIO_AF(GPIOI_PIN1, 0) | \
PIN_AFIO_AF(GPIOI_PIN2, 0) | \
PIN_AFIO_AF(GPIOI_PIN3, 0) | \
PIN_AFIO_AF(GPIOI_PIN4, 0) | \
PIN_AFIO_AF(GPIOI_PIN5, 0) | \
PIN_AFIO_AF(GPIOI_PIN6, 0) | \
PIN_AFIO_AF(GPIOI_PIN7, 0))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
PIN_AFIO_AF(GPIOI_LED3, 0) | \
PIN_AFIO_AF(GPIOI_PIN10, 0) | \
PIN_AFIO_AF(GPIOI_OTG_HS_ULPI_DIR, 10) |\
PIN_AFIO_AF(GPIOI_PIN12, 0) | \
PIN_AFIO_AF(GPIOI_PIN13, 0) | \
PIN_AFIO_AF(GPIOI_PIN14, 0) | \
PIN_AFIO_AF(GPIOI_PIN15, 0))


#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */

#endif /* _BOARD_H_ */

Link to comment
Share on other sites

I didn't take a look at the datasheet nor your complete code but what I see directly is that this:


#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x08000000)) /* RS = 1 */

seems to be wrong. The FSMC Bank you're using starts at 0x60000000 and therefore the address of your RS pin cannot be below that. How did you get to 0x08000000 anyway? That's actually the start address of the flash.

~ Tectu

Link to comment
Share on other sites

Now i'm using ST's code to define GDISP_REG & _DATA.

typedef struct
{
volatile uint16_t LCD_REG;
volatile uint16_t LCD_RAM;
} LCD_TypeDef;

#define LCD_BASE ((uint32_t)(0x60000000 | 0x08000000))
#define LCD ((LCD_TypeDef *) LCD_BASE)

#define GDISP_REG LCD->LCD_REG
#define GDISP_RAM LCD->LCD_RAM

Link to comment
Share on other sites

Does it work?

Generally, one should read Tectu's post again: either of these two addresses should have 0x60000000 as a 'base'. Usually you set GDISP_REG to 0x60000000 and GDISP_RAM to (0x60000000 | flag), where 'flag' is a mask that says to which pin is your RS line hooked. For example, in SSD2119 I have RS (DC) pin on FSMC_A19, so I set GDISP_RAM to 0x60100000.

Link to comment
Share on other sites

Ouch. As I understand the problem, RS should be tied to a high adress pin.

The FSMC of your microcontroller is just an external memory interface. Writing to it (especially with DMA) will increase the memory pointer (which results in changing adress pins).

A0 is therefore a bad choice for RS as it will go 0-1-0-1-0-1-0-1 when writing multiple bytes.

Link to comment
Share on other sites

What happens with the adress when you access any kind of memory? let's have a look

Reading/writing 8 Bytes from a memory address:


A0 A1 A2 A3 ...
0 0 0 0
1 0 0 0
0 1 0 0
1 1 0 0
0 0 1 0
1 0 1 0
0 1 1 0
1 1 1 0

As you can see, A0 will alternate for every byte you're accessing. Now, open the datasheet of your display controller and read the description of the RS pin.

Putting it to A0 will just fail as you keep switching it, even if you're writing plain image data!

Using an address pin for RS a neat little "trick" to map image data as well as control data to your controllers memory space without having to manually switch a GPIO.

But it has to be a high address pin (at least, the image data for your whole screen must need less address signals!)

Link to comment
Share on other sites

Hi all :)

How was your weekend ?

So.. I tested with

#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60000001)) /* RS = 1 */

but i'm no more able to read the 0x00 register wich should contains 0x9325...

Another idea ?

Link to comment
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
×
×
  • Create New...