NewHere94

I tried the last few weeks to build a new project with chibiOS 3.0 but I couldn't get it worked. The compiler says that some files are always missing. As soon as I found the missing file, there is a new missing file. Isn't there any way to get it worked with chibiOS 2.0? Does anyone successfully build a ugfx Project with the embest board and the stm32f407VG microcontroller using chibiOS2.0?

Ok, Thank you very much. I will try to get it work with ChibiOS V3.

I had problems with implementing Widgets (like a button), which is coupled with ginput. I started my project with the basic demo and then I added text an Image (with GDISP). That went fine. After that I wanted to implement an Widget. And then I ran into some Problems. I had no compiler errors but the dispaly always stayed black. When I debugged everything trough, the debugger halted always after executing a command. So I enabled some Debug Options. After that the Debugger stops at. #if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) /** * @brief Public trace buffer. */ ch_trace_buffer_t dbg_trace_buffer; /** * @brief Trace circular buffer subsystem initialization. * @note Internal use only. */ void _trace_init(void) { dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE; dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; } /** * @brief Inserts in the circular debug trace buffer a context switch record. * * @param[in] otp the thread being switched out * * @notapi */ void dbg_trace(Thread *otp) { dbg_trace_buffer.tb_ptr->se_time = chTimeNow(); dbg_trace_buffer.tb_ptr->se_tp = currp; dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; if (++dbg_trace_buffer.tb_ptr >= &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE]) dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; } #endif /* CH_DBG_ENABLE_TRACE */ Because I thought it should be an ChibiOS problems, I asked the ChibiOS Community. They told me that ChibiOS V2 is to old and that i should use V3. I think it should be a problem with stacksize or an overflow somewhere. But I have no idea where.

I started my first Project with ChibiOS V2 but I ran into a lot of problems. So I started a new Project with V3. Ok, thanks... I will try it.

No, It's the first time that I am working with ChibiOS.

When I look at the board.h (supplied by ChibiOS 3.x) I couldn't find any Option to enable? /* ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ #ifndef _BOARD_H_ #define _BOARD_H_ /* * Setup for STMicroelectronics STM32F4-Discovery board. */ /* * Board identifier. */ #define BOARD_ST_STM32F4_DISCOVERY #define BOARD_NAME "STMicroelectronics STM32F4-Discovery" /* * Board oscillators-related settings. * NOTE: LSE not fitted. */ #if !defined(STM32_LSECLK) #define STM32_LSECLK 0U #endif #if !defined(STM32_HSECLK) #define STM32_HSECLK 8000000U #endif /* * Board voltages. * Required for performance limits calculation. */ #define STM32_VDD 300U /* * MCU type as defined in the ST header. */ #define STM32F407xx /* * IO pins assignments. */ #define GPIOA_BUTTON 0U #define GPIOA_PIN1 1U #define GPIOA_PIN2 2U #define GPIOA_PIN3 3U #define GPIOA_LRCK 4U #define GPIOA_SPC 5U #define GPIOA_SDO 6U #define GPIOA_SDI 7U #define GPIOA_PIN8 8U #define GPIOA_VBUS_FS 9U #define GPIOA_OTG_FS_ID 10U #define GPIOA_OTG_FS_DM 11U #define GPIOA_OTG_FS_DP 12U #define GPIOA_SWDIO 13U #define GPIOA_SWCLK 14U #define GPIOA_PIN15 15U #define GPIOB_PIN0 0U #define GPIOB_PIN1 1U #define GPIOB_PIN2 2U #define GPIOB_SWO 3U #define GPIOB_PIN4 4U #define GPIOB_PIN5 5U #define GPIOB_SCL 6U #define GPIOB_PIN7 7U #define GPIOB_PIN8 8U #define GPIOB_SDA 9U #define GPIOB_CLK_IN 10U #define GPIOB_PIN11 11U #define GPIOB_PIN12 12U #define GPIOB_PIN13 13U #define GPIOB_PIN14 14U #define GPIOB_PIN15 15U #define GPIOC_OTG_FS_POWER_ON 0U #define GPIOC_PIN1 1U #define GPIOC_PIN2 2U #define GPIOC_PDM_OUT 3U #define GPIOC_PIN4 4U #define GPIOC_PIN5 5U #define GPIOC_PIN6 6U #define GPIOC_MCLK 7U #define GPIOC_PIN8 8U #define GPIOC_PIN9 9U #define GPIOC_SCLK 10U #define GPIOC_PIN11 11U #define GPIOC_SDIN 12U #define GPIOC_PIN13 13U #define GPIOC_PIN14 14U #define GPIOC_PIN15 15U #define GPIOD_PIN0 0U #define GPIOD_PIN1 1U #define GPIOD_PIN2 2U #define GPIOD_PIN3 3U #define GPIOD_RESET 4U #define GPIOD_OVER_CURRENT 5U #define GPIOD_PIN6 6U #define GPIOD_PIN7 7U #define GPIOD_PIN8 8U #define GPIOD_PIN9 9U #define GPIOD_PIN10 10U #define GPIOD_PIN11 11U #define GPIOD_LED4 12U #define GPIOD_LED3 13U #define GPIOD_LED5 14U #define GPIOD_LED6 15U #define GPIOE_INT1 0U #define GPIOE_INT2 1U #define GPIOE_PIN2 2U #define GPIOE_CS_SPI 3U #define GPIOE_PIN4 4U #define GPIOE_PIN5 5U #define GPIOE_PIN6 6U #define GPIOE_PIN7 7U #define GPIOE_PIN8 8U #define GPIOE_PIN9 9U #define GPIOE_PIN10 10U #define GPIOE_PIN11 11U #define GPIOE_PIN12 12U #define GPIOE_PIN13 13U #define GPIOE_PIN14 14U #define GPIOE_PIN15 15U #define GPIOF_PIN0 0U #define GPIOF_PIN1 1U #define GPIOF_PIN2 2U #define GPIOF_PIN3 3U #define GPIOF_PIN4 4U #define GPIOF_PIN5 5U #define GPIOF_PIN6 6U #define GPIOF_PIN7 7U #define GPIOF_PIN8 8U #define GPIOF_PIN9 9U #define GPIOF_PIN10 10U #define GPIOF_PIN11 11U #define GPIOF_PIN12 12U #define GPIOF_PIN13 13U #define GPIOF_PIN14 14U #define GPIOF_PIN15 15U #define GPIOG_PIN0 0U #define GPIOG_PIN1 1U #define GPIOG_PIN2 2U #define GPIOG_PIN3 3U #define GPIOG_PIN4 4U #define GPIOG_PIN5 5U #define GPIOG_PIN6 6U #define GPIOG_PIN7 7U #define GPIOG_PIN8 8U #define GPIOG_PIN9 9U #define GPIOG_PIN10 10U #define GPIOG_PIN11 11U #define GPIOG_PIN12 12U #define GPIOG_PIN13 13U #define GPIOG_PIN14 14U #define GPIOG_PIN15 15U #define GPIOH_OSC_IN 0U #define GPIOH_OSC_OUT 1U #define GPIOH_PIN2 2U #define GPIOH_PIN3 3U #define GPIOH_PIN4 4U #define GPIOH_PIN5 5U #define GPIOH_PIN6 6U #define GPIOH_PIN7 7U #define GPIOH_PIN8 8U #define GPIOH_PIN9 9U #define GPIOH_PIN10 10U #define GPIOH_PIN11 11U #define GPIOH_PIN12 12U #define GPIOH_PIN13 13U #define GPIOH_PIN14 14U #define GPIOH_PIN15 15U #define GPIOI_PIN0 0U #define GPIOI_PIN1 1U #define GPIOI_PIN2 2U #define GPIOI_PIN3 3U #define GPIOI_PIN4 4U #define GPIOI_PIN5 5U #define GPIOI_PIN6 6U #define GPIOI_PIN7 7U #define GPIOI_PIN8 8U #define GPIOI_PIN9 9U #define GPIOI_PIN10 10U #define GPIOI_PIN11 11U #define GPIOI_PIN12 12U #define GPIOI_PIN13 13U #define GPIOI_PIN14 14U #define GPIOI_PIN15 15U /* * I/O ports initial setup, this configuration is established soon after reset * in the initialization code. * Please refer to the STM32 Reference Manual for details. */ #define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) #define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) #define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) #define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) #define PIN_ODR_LOW(n) (0U << (n)) #define PIN_ODR_HIGH(n) (1U << (n)) #define PIN_OTYPE_PUSHPULL(n) (0U << (n)) #define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) #define PIN_OSPEED_2M(n) (0U << ((n) * 2U)) #define PIN_OSPEED_25M(n) (1U << ((n) * 2U)) #define PIN_OSPEED_50M(n) (2U << ((n) * 2U)) #define PIN_OSPEED_100M(n) (3U << ((n) * 2U)) #define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) #define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) #define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) #define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) /* * GPIOA setup: * * PA0 - BUTTON (input floating). * PA1 - PIN1 (input pullup). * PA2 - PIN2 (input pullup). * PA3 - PIN3 (input pullup). * PA4 - LRCK (alternate 6). * PA5 - SPC (alternate 5). * PA6 - SDO (alternate 5). * PA7 - SDI (alternate 5). * PA8 - PIN8 (input pullup). * PA9 - VBUS_FS (input floating). * PA10 - OTG_FS_ID (alternate 10). * PA11 - OTG_FS_DM (alternate 10). * PA12 - OTG_FS_DP (alternate 10). * PA13 - SWDIO (alternate 0). * PA14 - SWCLK (alternate 0). * PA15 - PIN15 (input pullup). */ #define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ PIN_MODE_INPUT(GPIOA_PIN1) | \ PIN_MODE_INPUT(GPIOA_PIN2) | \ PIN_MODE_INPUT(GPIOA_PIN3) | \ PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ PIN_MODE_ALTERNATE(GPIOA_SPC) | \ PIN_MODE_ALTERNATE(GPIOA_SDO) | \ PIN_MODE_ALTERNATE(GPIOA_SDI) | \ PIN_MODE_INPUT(GPIOA_PIN8) | \ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ PIN_MODE_INPUT(GPIOA_PIN15)) #define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) #define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \ PIN_OSPEED_100M(GPIOA_PIN1) | \ PIN_OSPEED_100M(GPIOA_PIN2) | \ PIN_OSPEED_100M(GPIOA_PIN3) | \ PIN_OSPEED_100M(GPIOA_LRCK) | \ PIN_OSPEED_50M(GPIOA_SPC) | \ PIN_OSPEED_50M(GPIOA_SDO) | \ PIN_OSPEED_50M(GPIOA_SDI) | \ PIN_OSPEED_100M(GPIOA_PIN8) | \ PIN_OSPEED_100M(GPIOA_VBUS_FS) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ PIN_OSPEED_100M(GPIOA_SWDIO) | \ PIN_OSPEED_100M(GPIOA_SWCLK) | \ PIN_OSPEED_100M(GPIOA_PIN15)) #define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ PIN_PUPDR_FLOATING(GPIOA_SPC) | \ PIN_PUPDR_FLOATING(GPIOA_SDO) | \ PIN_PUPDR_FLOATING(GPIOA_SDI) | \ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ PIN_PUPDR_PULLUP(GPIOA_PIN15)) #define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ PIN_ODR_HIGH(GPIOA_PIN1) | \ PIN_ODR_HIGH(GPIOA_PIN2) | \ PIN_ODR_HIGH(GPIOA_PIN3) | \ PIN_ODR_HIGH(GPIOA_LRCK) | \ PIN_ODR_HIGH(GPIOA_SPC) | \ PIN_ODR_HIGH(GPIOA_SDO) | \ PIN_ODR_HIGH(GPIOA_SDI) | \ PIN_ODR_HIGH(GPIOA_PIN8) | \ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ PIN_ODR_HIGH(GPIOA_SWDIO) | \ PIN_ODR_HIGH(GPIOA_SWCLK) | \ PIN_ODR_HIGH(GPIOA_PIN15)) #define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ PIN_AFIO_AF(GPIOA_PIN1, 0) | \ PIN_AFIO_AF(GPIOA_PIN2, 0) | \ PIN_AFIO_AF(GPIOA_PIN3, 0) | \ PIN_AFIO_AF(GPIOA_LRCK, 6) | \ PIN_AFIO_AF(GPIOA_SPC, 5) | \ PIN_AFIO_AF(GPIOA_SDO, 5) | \ PIN_AFIO_AF(GPIOA_SDI, 5)) #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ PIN_AFIO_AF(GPIOA_PIN15, 0)) /* * GPIOB setup: * * PB0 - PIN0 (input pullup). * PB1 - PIN1 (input pullup). * PB2 - PIN2 (input pullup). * PB3 - SWO (alternate 0). * PB4 - PIN4 (input pullup). * PB5 - PIN5 (input pullup). * PB6 - SCL (alternate 4). * PB7 - PIN7 (input pullup). * PB8 - PIN8 (input pullup). * PB9 - SDA (alternate 4). * PB10 - CLK_IN (input pullup). * PB11 - PIN11 (input pullup). * PB12 - PIN12 (input pullup). * PB13 - PIN13 (input pullup). * PB14 - PIN14 (input pullup). * PB15 - PIN15 (input pullup). */ #define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ PIN_MODE_INPUT(GPIOB_PIN1) | \ PIN_MODE_INPUT(GPIOB_PIN2) | \ PIN_MODE_ALTERNATE(GPIOB_SWO) | \ PIN_MODE_INPUT(GPIOB_PIN4) | \ PIN_MODE_INPUT(GPIOB_PIN5) | \ PIN_MODE_ALTERNATE(GPIOB_SCL) | \ PIN_MODE_INPUT(GPIOB_PIN7) | \ PIN_MODE_INPUT(GPIOB_PIN8) | \ PIN_MODE_ALTERNATE(GPIOB_SDA) | \ PIN_MODE_INPUT(GPIOB_CLK_IN) | \ PIN_MODE_INPUT(GPIOB_PIN11) | \ PIN_MODE_INPUT(GPIOB_PIN12) | \ PIN_MODE_INPUT(GPIOB_PIN13) | \ PIN_MODE_INPUT(GPIOB_PIN14) | \ PIN_MODE_INPUT(GPIOB_PIN15)) #define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \ PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) #define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ PIN_OSPEED_100M(GPIOB_PIN1) | \ PIN_OSPEED_100M(GPIOB_PIN2) | \ PIN_OSPEED_100M(GPIOB_SWO) | \ PIN_OSPEED_100M(GPIOB_PIN4) | \ PIN_OSPEED_100M(GPIOB_PIN5) | \ PIN_OSPEED_100M(GPIOB_SCL) | \ PIN_OSPEED_100M(GPIOB_PIN7) | \ PIN_OSPEED_100M(GPIOB_PIN8) | \ PIN_OSPEED_100M(GPIOB_SDA) | \ PIN_OSPEED_100M(GPIOB_CLK_IN) | \ PIN_OSPEED_100M(GPIOB_PIN11) | \ PIN_OSPEED_100M(GPIOB_PIN12) | \ PIN_OSPEED_100M(GPIOB_PIN13) | \ PIN_OSPEED_100M(GPIOB_PIN14) | \ PIN_OSPEED_100M(GPIOB_PIN15)) #define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ PIN_PUPDR_FLOATING(GPIOB_SWO) | \ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ PIN_PUPDR_FLOATING(GPIOB_SCL) | \ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ PIN_PUPDR_FLOATING(GPIOB_SDA) | \ PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ PIN_PUPDR_PULLUP(GPIOB_PIN15)) #define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ PIN_ODR_HIGH(GPIOB_PIN1) | \ PIN_ODR_HIGH(GPIOB_PIN2) | \ PIN_ODR_HIGH(GPIOB_SWO) | \ PIN_ODR_HIGH(GPIOB_PIN4) | \ PIN_ODR_HIGH(GPIOB_PIN5) | \ PIN_ODR_HIGH(GPIOB_SCL) | \ PIN_ODR_HIGH(GPIOB_PIN7) | \ PIN_ODR_HIGH(GPIOB_PIN8) | \ PIN_ODR_HIGH(GPIOB_SDA) | \ PIN_ODR_HIGH(GPIOB_CLK_IN) | \ PIN_ODR_HIGH(GPIOB_PIN11) | \ PIN_ODR_HIGH(GPIOB_PIN12) | \ PIN_ODR_HIGH(GPIOB_PIN13) | \ PIN_ODR_HIGH(GPIOB_PIN14) | \ PIN_ODR_HIGH(GPIOB_PIN15)) #define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ PIN_AFIO_AF(GPIOB_PIN1, 0) | \ PIN_AFIO_AF(GPIOB_PIN2, 0) | \ PIN_AFIO_AF(GPIOB_SWO, 0) | \ PIN_AFIO_AF(GPIOB_PIN4, 0) | \ PIN_AFIO_AF(GPIOB_PIN5, 0) | \ PIN_AFIO_AF(GPIOB_SCL, 4) | \ PIN_AFIO_AF(GPIOB_PIN7, 0)) #define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ PIN_AFIO_AF(GPIOB_SDA, 4) | \ PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \ PIN_AFIO_AF(GPIOB_PIN11, 0) | \ PIN_AFIO_AF(GPIOB_PIN12, 0) | \ PIN_AFIO_AF(GPIOB_PIN13, 0) | \ PIN_AFIO_AF(GPIOB_PIN14, 0) | \ PIN_AFIO_AF(GPIOB_PIN15, 0)) /* * GPIOC setup: * * PC0 - OTG_FS_POWER_ON (output pushpull maximum). * PC1 - PIN1 (input pullup). * PC2 - PIN2 (input pullup). * PC3 - PDM_OUT (input pullup). * PC4 - PIN4 (input pullup). * PC5 - PIN5 (input pullup). * PC6 - PIN6 (input pullup). * PC7 - MCLK (alternate 6). * PC8 - PIN8 (input pullup). * PC9 - PIN9 (input pullup). * PC10 - SCLK (alternate 6). * PC11 - PIN11 (input pullup). * PC12 - SDIN (alternate 6). * PC13 - PIN13 (input pullup). * PC14 - PIN14 (input pullup). * PC15 - PIN15 (input pullup). */ #define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ PIN_MODE_INPUT(GPIOC_PIN1) | \ PIN_MODE_INPUT(GPIOC_PIN2) | \ PIN_MODE_INPUT(GPIOC_PDM_OUT) | \ PIN_MODE_INPUT(GPIOC_PIN4) | \ PIN_MODE_INPUT(GPIOC_PIN5) | \ PIN_MODE_INPUT(GPIOC_PIN6) | \ PIN_MODE_ALTERNATE(GPIOC_MCLK) | \ PIN_MODE_INPUT(GPIOC_PIN8) | \ PIN_MODE_INPUT(GPIOC_PIN9) | \ PIN_MODE_ALTERNATE(GPIOC_SCLK) | \ PIN_MODE_INPUT(GPIOC_PIN11) | \ PIN_MODE_ALTERNATE(GPIOC_SDIN) | \ PIN_MODE_INPUT(GPIOC_PIN13) | \ PIN_MODE_INPUT(GPIOC_PIN14) | \ PIN_MODE_INPUT(GPIOC_PIN15)) #define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOC_SCLK) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOC_SDIN) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) #define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\ PIN_OSPEED_100M(GPIOC_PIN1) | \ PIN_OSPEED_100M(GPIOC_PIN2) | \ PIN_OSPEED_100M(GPIOC_PDM_OUT) | \ PIN_OSPEED_100M(GPIOC_PIN4) | \ PIN_OSPEED_100M(GPIOC_PIN5) | \ PIN_OSPEED_100M(GPIOC_PIN6) | \ PIN_OSPEED_100M(GPIOC_MCLK) | \ PIN_OSPEED_100M(GPIOC_PIN8) | \ PIN_OSPEED_100M(GPIOC_PIN9) | \ PIN_OSPEED_100M(GPIOC_SCLK) | \ PIN_OSPEED_100M(GPIOC_PIN11) | \ PIN_OSPEED_100M(GPIOC_SDIN) | \ PIN_OSPEED_100M(GPIOC_PIN13) | \ PIN_OSPEED_100M(GPIOC_PIN14) | \ PIN_OSPEED_100M(GPIOC_PIN15)) #define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ PIN_PUPDR_FLOATING(GPIOC_MCLK) | \ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ PIN_PUPDR_FLOATING(GPIOC_SCLK) | \ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ PIN_PUPDR_FLOATING(GPIOC_SDIN) | \ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ PIN_PUPDR_PULLUP(GPIOC_PIN15)) #define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ PIN_ODR_HIGH(GPIOC_PIN1) | \ PIN_ODR_HIGH(GPIOC_PIN2) | \ PIN_ODR_HIGH(GPIOC_PDM_OUT) | \ PIN_ODR_HIGH(GPIOC_PIN4) | \ PIN_ODR_HIGH(GPIOC_PIN5) | \ PIN_ODR_HIGH(GPIOC_PIN6) | \ PIN_ODR_HIGH(GPIOC_MCLK) | \ PIN_ODR_HIGH(GPIOC_PIN8) | \ PIN_ODR_HIGH(GPIOC_PIN9) | \ PIN_ODR_HIGH(GPIOC_SCLK) | \ PIN_ODR_HIGH(GPIOC_PIN11) | \ PIN_ODR_HIGH(GPIOC_SDIN) | \ PIN_ODR_HIGH(GPIOC_PIN13) | \ PIN_ODR_HIGH(GPIOC_PIN14) | \ PIN_ODR_HIGH(GPIOC_PIN15)) #define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\ PIN_AFIO_AF(GPIOC_PIN1, 0) | \ PIN_AFIO_AF(GPIOC_PIN2, 0) | \ PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \ PIN_AFIO_AF(GPIOC_PIN4, 0) | \ PIN_AFIO_AF(GPIOC_PIN5, 0) | \ PIN_AFIO_AF(GPIOC_PIN6, 0) | \ PIN_AFIO_AF(GPIOC_MCLK, 6)) #define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ PIN_AFIO_AF(GPIOC_PIN9, 0) | \ PIN_AFIO_AF(GPIOC_SCLK, 6) | \ PIN_AFIO_AF(GPIOC_PIN11, 0) | \ PIN_AFIO_AF(GPIOC_SDIN, 6) | \ PIN_AFIO_AF(GPIOC_PIN13, 0) | \ PIN_AFIO_AF(GPIOC_PIN14, 0) | \ PIN_AFIO_AF(GPIOC_PIN15, 0)) /* * GPIOD setup: * * PD0 - PIN0 (input pullup). * PD1 - PIN1 (input pullup). * PD2 - PIN2 (input pullup). * PD3 - PIN3 (input pullup). * PD4 - RESET (output pushpull maximum). * PD5 - OVER_CURRENT (input floating). * PD6 - PIN6 (input pullup). * PD7 - PIN7 (input pullup). * PD8 - PIN8 (input pullup). * PD9 - PIN9 (input pullup). * PD10 - PIN10 (input pullup). * PD11 - PIN11 (input pullup). * PD12 - LED4 (output pushpull maximum). * PD13 - LED3 (output pushpull maximum). * PD14 - LED5 (output pushpull maximum). * PD15 - LED6 (output pushpull maximum). */ #define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ PIN_MODE_INPUT(GPIOD_PIN1) | \ PIN_MODE_INPUT(GPIOD_PIN2) | \ PIN_MODE_INPUT(GPIOD_PIN3) | \ PIN_MODE_OUTPUT(GPIOD_RESET) | \ PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ PIN_MODE_INPUT(GPIOD_PIN6) | \ PIN_MODE_INPUT(GPIOD_PIN7) | \ PIN_MODE_INPUT(GPIOD_PIN8) | \ PIN_MODE_INPUT(GPIOD_PIN9) | \ PIN_MODE_INPUT(GPIOD_PIN10) | \ PIN_MODE_INPUT(GPIOD_PIN11) | \ PIN_MODE_OUTPUT(GPIOD_LED4) | \ PIN_MODE_OUTPUT(GPIOD_LED3) | \ PIN_MODE_OUTPUT(GPIOD_LED5) | \ PIN_MODE_OUTPUT(GPIOD_LED6)) #define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED6)) #define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ PIN_OSPEED_100M(GPIOD_PIN1) | \ PIN_OSPEED_100M(GPIOD_PIN2) | \ PIN_OSPEED_100M(GPIOD_PIN3) | \ PIN_OSPEED_100M(GPIOD_RESET) | \ PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \ PIN_OSPEED_100M(GPIOD_PIN6) | \ PIN_OSPEED_100M(GPIOD_PIN7) | \ PIN_OSPEED_100M(GPIOD_PIN8) | \ PIN_OSPEED_100M(GPIOD_PIN9) | \ PIN_OSPEED_100M(GPIOD_PIN10) | \ PIN_OSPEED_100M(GPIOD_PIN11) | \ PIN_OSPEED_100M(GPIOD_LED4) | \ PIN_OSPEED_100M(GPIOD_LED3) | \ PIN_OSPEED_100M(GPIOD_LED5) | \ PIN_OSPEED_100M(GPIOD_LED6)) #define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_RESET) | \ PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ PIN_PUPDR_FLOATING(GPIOD_LED4) | \ PIN_PUPDR_FLOATING(GPIOD_LED3) | \ PIN_PUPDR_FLOATING(GPIOD_LED5) | \ PIN_PUPDR_FLOATING(GPIOD_LED6)) #define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ PIN_ODR_HIGH(GPIOD_PIN1) | \ PIN_ODR_HIGH(GPIOD_PIN2) | \ PIN_ODR_HIGH(GPIOD_PIN3) | \ PIN_ODR_HIGH(GPIOD_RESET) | \ PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ PIN_ODR_HIGH(GPIOD_PIN6) | \ PIN_ODR_HIGH(GPIOD_PIN7) | \ PIN_ODR_HIGH(GPIOD_PIN8) | \ PIN_ODR_HIGH(GPIOD_PIN9) | \ PIN_ODR_HIGH(GPIOD_PIN10) | \ PIN_ODR_HIGH(GPIOD_PIN11) | \ PIN_ODR_LOW(GPIOD_LED4) | \ PIN_ODR_LOW(GPIOD_LED3) | \ PIN_ODR_LOW(GPIOD_LED5) | \ PIN_ODR_LOW(GPIOD_LED6)) #define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ PIN_AFIO_AF(GPIOD_PIN1, 0) | \ PIN_AFIO_AF(GPIOD_PIN2, 0) | \ PIN_AFIO_AF(GPIOD_PIN3, 0) | \ PIN_AFIO_AF(GPIOD_RESET, 0) | \ PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \ PIN_AFIO_AF(GPIOD_PIN6, 0) | \ PIN_AFIO_AF(GPIOD_PIN7, 0)) #define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ PIN_AFIO_AF(GPIOD_PIN9, 0) | \ PIN_AFIO_AF(GPIOD_PIN10, 0) | \ PIN_AFIO_AF(GPIOD_PIN11, 0) | \ PIN_AFIO_AF(GPIOD_LED4, 0) | \ PIN_AFIO_AF(GPIOD_LED3, 0) | \ PIN_AFIO_AF(GPIOD_LED5, 0) | \ PIN_AFIO_AF(GPIOD_LED6, 0)) /* * GPIOE setup: * * PE0 - INT1 (input floating). * PE1 - INT2 (input floating). * PE2 - PIN2 (input floating). * PE3 - CS_SPI (output pushpull maximum). * PE4 - PIN4 (input floating). * PE5 - PIN5 (input floating). * PE6 - PIN6 (input floating). * PE7 - PIN7 (input floating). * PE8 - PIN8 (input floating). * PE9 - PIN9 (input floating). * PE10 - PIN10 (input floating). * PE11 - PIN11 (input floating). * PE12 - PIN12 (input floating). * PE13 - PIN13 (input floating). * PE14 - PIN14 (input floating). * PE15 - PIN15 (input floating). */ #define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ PIN_MODE_INPUT(GPIOE_INT2) | \ PIN_MODE_INPUT(GPIOE_PIN2) | \ PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \ PIN_MODE_INPUT(GPIOE_PIN4) | \ PIN_MODE_INPUT(GPIOE_PIN5) | \ PIN_MODE_INPUT(GPIOE_PIN6) | \ PIN_MODE_INPUT(GPIOE_PIN7) | \ PIN_MODE_INPUT(GPIOE_PIN8) | \ PIN_MODE_INPUT(GPIOE_PIN9) | \ PIN_MODE_INPUT(GPIOE_PIN10) | \ PIN_MODE_INPUT(GPIOE_PIN11) | \ PIN_MODE_INPUT(GPIOE_PIN12) | \ PIN_MODE_INPUT(GPIOE_PIN13) | \ PIN_MODE_INPUT(GPIOE_PIN14) | \ PIN_MODE_INPUT(GPIOE_PIN15)) #define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \ PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) #define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \ PIN_OSPEED_100M(GPIOE_INT2) | \ PIN_OSPEED_100M(GPIOE_PIN2) | \ PIN_OSPEED_100M(GPIOE_CS_SPI) | \ PIN_OSPEED_100M(GPIOE_PIN4) | \ PIN_OSPEED_100M(GPIOE_PIN5) | \ PIN_OSPEED_100M(GPIOE_PIN6) | \ PIN_OSPEED_100M(GPIOE_PIN7) | \ PIN_OSPEED_100M(GPIOE_PIN8) | \ PIN_OSPEED_100M(GPIOE_PIN9) | \ PIN_OSPEED_100M(GPIOE_PIN10) | \ PIN_OSPEED_100M(GPIOE_PIN11) | \ PIN_OSPEED_100M(GPIOE_PIN12) | \ PIN_OSPEED_100M(GPIOE_PIN13) | \ PIN_OSPEED_100M(GPIOE_PIN14) | \ PIN_OSPEED_100M(GPIOE_PIN15)) #define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \ PIN_PUPDR_FLOATING(GPIOE_INT2) | \ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ PIN_PUPDR_FLOATING(GPIOE_PIN15)) #define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \ PIN_ODR_HIGH(GPIOE_INT2) | \ PIN_ODR_HIGH(GPIOE_PIN2) | \ PIN_ODR_HIGH(GPIOE_CS_SPI) | \ PIN_ODR_HIGH(GPIOE_PIN4) | \ PIN_ODR_HIGH(GPIOE_PIN5) | \ PIN_ODR_HIGH(GPIOE_PIN6) | \ PIN_ODR_HIGH(GPIOE_PIN7) | \ PIN_ODR_HIGH(GPIOE_PIN8) | \ PIN_ODR_HIGH(GPIOE_PIN9) | \ PIN_ODR_HIGH(GPIOE_PIN10) | \ PIN_ODR_HIGH(GPIOE_PIN11) | \ PIN_ODR_HIGH(GPIOE_PIN12) | \ PIN_ODR_HIGH(GPIOE_PIN13) | \ PIN_ODR_HIGH(GPIOE_PIN14) | \ PIN_ODR_HIGH(GPIOE_PIN15)) #define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \ PIN_AFIO_AF(GPIOE_INT2, 0) | \ PIN_AFIO_AF(GPIOE_PIN2, 0) | \ PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \ PIN_AFIO_AF(GPIOE_PIN4, 0) | \ PIN_AFIO_AF(GPIOE_PIN5, 0) | \ PIN_AFIO_AF(GPIOE_PIN6, 0) | \ PIN_AFIO_AF(GPIOE_PIN7, 0)) #define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ PIN_AFIO_AF(GPIOE_PIN9, 0) | \ PIN_AFIO_AF(GPIOE_PIN10, 0) | \ PIN_AFIO_AF(GPIOE_PIN11, 0) | \ PIN_AFIO_AF(GPIOE_PIN12, 0) | \ PIN_AFIO_AF(GPIOE_PIN13, 0) | \ PIN_AFIO_AF(GPIOE_PIN14, 0) | \ PIN_AFIO_AF(GPIOE_PIN15, 0)) /* * GPIOF setup: * * PF0 - PIN0 (input floating). * PF1 - PIN1 (input floating). * PF2 - PIN2 (input floating). * PF3 - PIN3 (input floating). * PF4 - PIN4 (input floating). * PF5 - PIN5 (input floating). * PF6 - PIN6 (input floating). * PF7 - PIN7 (input floating). * PF8 - PIN8 (input floating). * PF9 - PIN9 (input floating). * PF10 - PIN10 (input floating). * PF11 - PIN11 (input floating). * PF12 - PIN12 (input floating). * PF13 - PIN13 (input floating). * PF14 - PIN14 (input floating). * PF15 - PIN15 (input floating). */ #define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ PIN_MODE_INPUT(GPIOF_PIN1) | \ PIN_MODE_INPUT(GPIOF_PIN2) | \ PIN_MODE_INPUT(GPIOF_PIN3) | \ PIN_MODE_INPUT(GPIOF_PIN4) | \ PIN_MODE_INPUT(GPIOF_PIN5) | \ PIN_MODE_INPUT(GPIOF_PIN6) | \ PIN_MODE_INPUT(GPIOF_PIN7) | \ PIN_MODE_INPUT(GPIOF_PIN8) | \ PIN_MODE_INPUT(GPIOF_PIN9) | \ PIN_MODE_INPUT(GPIOF_PIN10) | \ PIN_MODE_INPUT(GPIOF_PIN11) | \ PIN_MODE_INPUT(GPIOF_PIN12) | \ PIN_MODE_INPUT(GPIOF_PIN13) | \ PIN_MODE_INPUT(GPIOF_PIN14) | \ PIN_MODE_INPUT(GPIOF_PIN15)) #define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) #define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ PIN_OSPEED_100M(GPIOF_PIN1) | \ PIN_OSPEED_100M(GPIOF_PIN2) | \ PIN_OSPEED_100M(GPIOF_PIN3) | \ PIN_OSPEED_100M(GPIOF_PIN4) | \ PIN_OSPEED_100M(GPIOF_PIN5) | \ PIN_OSPEED_100M(GPIOF_PIN6) | \ PIN_OSPEED_100M(GPIOF_PIN7) | \ PIN_OSPEED_100M(GPIOF_PIN8) | \ PIN_OSPEED_100M(GPIOF_PIN9) | \ PIN_OSPEED_100M(GPIOF_PIN10) | \ PIN_OSPEED_100M(GPIOF_PIN11) | \ PIN_OSPEED_100M(GPIOF_PIN12) | \ PIN_OSPEED_100M(GPIOF_PIN13) | \ PIN_OSPEED_100M(GPIOF_PIN14) | \ PIN_OSPEED_100M(GPIOF_PIN15)) #define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ PIN_PUPDR_FLOATING(GPIOF_PIN15)) #define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ PIN_ODR_HIGH(GPIOF_PIN1) | \ PIN_ODR_HIGH(GPIOF_PIN2) | \ PIN_ODR_HIGH(GPIOF_PIN3) | \ PIN_ODR_HIGH(GPIOF_PIN4) | \ PIN_ODR_HIGH(GPIOF_PIN5) | \ PIN_ODR_HIGH(GPIOF_PIN6) | \ PIN_ODR_HIGH(GPIOF_PIN7) | \ PIN_ODR_HIGH(GPIOF_PIN8) | \ PIN_ODR_HIGH(GPIOF_PIN9) | \ PIN_ODR_HIGH(GPIOF_PIN10) | \ PIN_ODR_HIGH(GPIOF_PIN11) | \ PIN_ODR_HIGH(GPIOF_PIN12) | \ PIN_ODR_HIGH(GPIOF_PIN13) | \ PIN_ODR_HIGH(GPIOF_PIN14) | \ PIN_ODR_HIGH(GPIOF_PIN15)) #define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ PIN_AFIO_AF(GPIOF_PIN1, 0) | \ PIN_AFIO_AF(GPIOF_PIN2, 0) | \ PIN_AFIO_AF(GPIOF_PIN3, 0) | \ PIN_AFIO_AF(GPIOF_PIN4, 0) | \ PIN_AFIO_AF(GPIOF_PIN5, 0) | \ PIN_AFIO_AF(GPIOF_PIN6, 0) | \ PIN_AFIO_AF(GPIOF_PIN7, 0)) #define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ PIN_AFIO_AF(GPIOF_PIN9, 0) | \ PIN_AFIO_AF(GPIOF_PIN10, 0) | \ PIN_AFIO_AF(GPIOF_PIN11, 0) | \ PIN_AFIO_AF(GPIOF_PIN12, 0) | \ PIN_AFIO_AF(GPIOF_PIN13, 0) | \ PIN_AFIO_AF(GPIOF_PIN14, 0) | \ PIN_AFIO_AF(GPIOF_PIN15, 0)) /* * GPIOG setup: * * PG0 - PIN0 (input floating). * PG1 - PIN1 (input floating). * PG2 - PIN2 (input floating). * PG3 - PIN3 (input floating). * PG4 - PIN4 (input floating). * PG5 - PIN5 (input floating). * PG6 - PIN6 (input floating). * PG7 - PIN7 (input floating). * PG8 - PIN8 (input floating). * PG9 - PIN9 (input floating). * PG10 - PIN10 (input floating). * PG11 - PIN11 (input floating). * PG12 - PIN12 (input floating). * PG13 - PIN13 (input floating). * PG14 - PIN14 (input floating). * PG15 - PIN15 (input floating). */ #define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ PIN_MODE_INPUT(GPIOG_PIN1) | \ PIN_MODE_INPUT(GPIOG_PIN2) | \ PIN_MODE_INPUT(GPIOG_PIN3) | \ PIN_MODE_INPUT(GPIOG_PIN4) | \ PIN_MODE_INPUT(GPIOG_PIN5) | \ PIN_MODE_INPUT(GPIOG_PIN6) | \ PIN_MODE_INPUT(GPIOG_PIN7) | \ PIN_MODE_INPUT(GPIOG_PIN8) | \ PIN_MODE_INPUT(GPIOG_PIN9) | \ PIN_MODE_INPUT(GPIOG_PIN10) | \ PIN_MODE_INPUT(GPIOG_PIN11) | \ PIN_MODE_INPUT(GPIOG_PIN12) | \ PIN_MODE_INPUT(GPIOG_PIN13) | \ PIN_MODE_INPUT(GPIOG_PIN14) | \ PIN_MODE_INPUT(GPIOG_PIN15)) #define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) #define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ PIN_OSPEED_100M(GPIOG_PIN1) | \ PIN_OSPEED_100M(GPIOG_PIN2) | \ PIN_OSPEED_100M(GPIOG_PIN3) | \ PIN_OSPEED_100M(GPIOG_PIN4) | \ PIN_OSPEED_100M(GPIOG_PIN5) | \ PIN_OSPEED_100M(GPIOG_PIN6) | \ PIN_OSPEED_100M(GPIOG_PIN7) | \ PIN_OSPEED_100M(GPIOG_PIN8) | \ PIN_OSPEED_100M(GPIOG_PIN9) | \ PIN_OSPEED_100M(GPIOG_PIN10) | \ PIN_OSPEED_100M(GPIOG_PIN11) | \ PIN_OSPEED_100M(GPIOG_PIN12) | \ PIN_OSPEED_100M(GPIOG_PIN13) | \ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ PIN_PUPDR_FLOATING(GPIOG_PIN15)) #define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ PIN_ODR_HIGH(GPIOG_PIN1) | \ PIN_ODR_HIGH(GPIOG_PIN2) | \ PIN_ODR_HIGH(GPIOG_PIN3) | \ PIN_ODR_HIGH(GPIOG_PIN4) | \ PIN_ODR_HIGH(GPIOG_PIN5) | \ PIN_ODR_HIGH(GPIOG_PIN6) | \ PIN_ODR_HIGH(GPIOG_PIN7) | \ PIN_ODR_HIGH(GPIOG_PIN8) | \ PIN_ODR_HIGH(GPIOG_PIN9) | \ PIN_ODR_HIGH(GPIOG_PIN10) | \ PIN_ODR_HIGH(GPIOG_PIN11) | \ PIN_ODR_HIGH(GPIOG_PIN12) | \ PIN_ODR_HIGH(GPIOG_PIN13) | \ PIN_ODR_HIGH(GPIOG_PIN14) | \ PIN_ODR_HIGH(GPIOG_PIN15)) #define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ PIN_AFIO_AF(GPIOG_PIN1, 0) | \ PIN_AFIO_AF(GPIOG_PIN2, 0) | \ PIN_AFIO_AF(GPIOG_PIN3, 0) | \ PIN_AFIO_AF(GPIOG_PIN4, 0) | \ PIN_AFIO_AF(GPIOG_PIN5, 0) | \ PIN_AFIO_AF(GPIOG_PIN6, 0) | \ PIN_AFIO_AF(GPIOG_PIN7, 0)) #define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ PIN_AFIO_AF(GPIOG_PIN9, 0) | \ PIN_AFIO_AF(GPIOG_PIN10, 0) | \ PIN_AFIO_AF(GPIOG_PIN11, 0) | \ PIN_AFIO_AF(GPIOG_PIN12, 0) | \ PIN_AFIO_AF(GPIOG_PIN13, 0) | \ PIN_AFIO_AF(GPIOG_PIN14, 0) | \ PIN_AFIO_AF(GPIOG_PIN15, 0)) /* * GPIOH setup: * * PH0 - OSC_IN (input floating). * PH1 - OSC_OUT (input floating). * PH2 - PIN2 (input floating). * PH3 - PIN3 (input floating). * PH4 - PIN4 (input floating). * PH5 - PIN5 (input floating). * PH6 - PIN6 (input floating). * PH7 - PIN7 (input floating). * PH8 - PIN8 (input floating). * PH9 - PIN9 (input floating). * PH10 - PIN10 (input floating). * PH11 - PIN11 (input floating). * PH12 - PIN12 (input floating). * PH13 - PIN13 (input floating). * PH14 - PIN14 (input floating). * PH15 - PIN15 (input floating). */ #define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ PIN_MODE_INPUT(GPIOH_PIN2) | \ PIN_MODE_INPUT(GPIOH_PIN3) | \ PIN_MODE_INPUT(GPIOH_PIN4) | \ PIN_MODE_INPUT(GPIOH_PIN5) | \ PIN_MODE_INPUT(GPIOH_PIN6) | \ PIN_MODE_INPUT(GPIOH_PIN7) | \ PIN_MODE_INPUT(GPIOH_PIN8) | \ PIN_MODE_INPUT(GPIOH_PIN9) | \ PIN_MODE_INPUT(GPIOH_PIN10) | \ PIN_MODE_INPUT(GPIOH_PIN11) | \ PIN_MODE_INPUT(GPIOH_PIN12) | \ PIN_MODE_INPUT(GPIOH_PIN13) | \ PIN_MODE_INPUT(GPIOH_PIN14) | \ PIN_MODE_INPUT(GPIOH_PIN15)) #define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) #define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ PIN_OSPEED_100M(GPIOH_PIN2) | \ PIN_OSPEED_100M(GPIOH_PIN3) | \ PIN_OSPEED_100M(GPIOH_PIN4) | \ PIN_OSPEED_100M(GPIOH_PIN5) | \ PIN_OSPEED_100M(GPIOH_PIN6) | \ PIN_OSPEED_100M(GPIOH_PIN7) | \ PIN_OSPEED_100M(GPIOH_PIN8) | \ PIN_OSPEED_100M(GPIOH_PIN9) | \ PIN_OSPEED_100M(GPIOH_PIN10) | \ PIN_OSPEED_100M(GPIOH_PIN11) | \ PIN_OSPEED_100M(GPIOH_PIN12) | \ PIN_OSPEED_100M(GPIOH_PIN13) | \ PIN_OSPEED_100M(GPIOH_PIN14) | \ PIN_OSPEED_100M(GPIOH_PIN15)) #define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ PIN_PUPDR_FLOATING(GPIOH_PIN15)) #define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ PIN_ODR_HIGH(GPIOH_PIN2) | \ PIN_ODR_HIGH(GPIOH_PIN3) | \ PIN_ODR_HIGH(GPIOH_PIN4) | \ PIN_ODR_HIGH(GPIOH_PIN5) | \ PIN_ODR_HIGH(GPIOH_PIN6) | \ PIN_ODR_HIGH(GPIOH_PIN7) | \ PIN_ODR_HIGH(GPIOH_PIN8) | \ PIN_ODR_HIGH(GPIOH_PIN9) | \ PIN_ODR_HIGH(GPIOH_PIN10) | \ PIN_ODR_HIGH(GPIOH_PIN11) | \ PIN_ODR_HIGH(GPIOH_PIN12) | \ PIN_ODR_HIGH(GPIOH_PIN13) | \ PIN_ODR_HIGH(GPIOH_PIN14) | \ PIN_ODR_HIGH(GPIOH_PIN15)) #define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ PIN_AFIO_AF(GPIOH_PIN2, 0) | \ PIN_AFIO_AF(GPIOH_PIN3, 0) | \ PIN_AFIO_AF(GPIOH_PIN4, 0) | \ PIN_AFIO_AF(GPIOH_PIN5, 0) | \ PIN_AFIO_AF(GPIOH_PIN6, 0) | \ PIN_AFIO_AF(GPIOH_PIN7, 0)) #define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ PIN_AFIO_AF(GPIOH_PIN9, 0) | \ PIN_AFIO_AF(GPIOH_PIN10, 0) | \ PIN_AFIO_AF(GPIOH_PIN11, 0) | \ PIN_AFIO_AF(GPIOH_PIN12, 0) | \ PIN_AFIO_AF(GPIOH_PIN13, 0) | \ PIN_AFIO_AF(GPIOH_PIN14, 0) | \ PIN_AFIO_AF(GPIOH_PIN15, 0)) /* * GPIOI setup: * * PI0 - PIN0 (input floating). * PI1 - PIN1 (input floating). * PI2 - PIN2 (input floating). * PI3 - PIN3 (input floating). * PI4 - PIN4 (input floating). * PI5 - PIN5 (input floating). * PI6 - PIN6 (input floating). * PI7 - PIN7 (input floating). * PI8 - PIN8 (input floating). * PI9 - PIN9 (input floating). * PI10 - PIN10 (input floating). * PI11 - PIN11 (input floating). * PI12 - PIN12 (input floating). * PI13 - PIN13 (input floating). * PI14 - PIN14 (input floating). * PI15 - PIN15 (input floating). */ #define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ PIN_MODE_INPUT(GPIOI_PIN1) | \ PIN_MODE_INPUT(GPIOI_PIN2) | \ PIN_MODE_INPUT(GPIOI_PIN3) | \ PIN_MODE_INPUT(GPIOI_PIN4) | \ PIN_MODE_INPUT(GPIOI_PIN5) | \ PIN_MODE_INPUT(GPIOI_PIN6) | \ PIN_MODE_INPUT(GPIOI_PIN7) | \ PIN_MODE_INPUT(GPIOI_PIN8) | \ PIN_MODE_INPUT(GPIOI_PIN9) | \ PIN_MODE_INPUT(GPIOI_PIN10) | \ PIN_MODE_INPUT(GPIOI_PIN11) | \ PIN_MODE_INPUT(GPIOI_PIN12) | \ PIN_MODE_INPUT(GPIOI_PIN13) | \ PIN_MODE_INPUT(GPIOI_PIN14) | \ PIN_MODE_INPUT(GPIOI_PIN15)) #define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) #define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ PIN_OSPEED_100M(GPIOI_PIN1) | \ PIN_OSPEED_100M(GPIOI_PIN2) | \ PIN_OSPEED_100M(GPIOI_PIN3) | \ PIN_OSPEED_100M(GPIOI_PIN4) | \ PIN_OSPEED_100M(GPIOI_PIN5) | \ PIN_OSPEED_100M(GPIOI_PIN6) | \ PIN_OSPEED_100M(GPIOI_PIN7) | \ PIN_OSPEED_100M(GPIOI_PIN8) | \ PIN_OSPEED_100M(GPIOI_PIN9) | \ PIN_OSPEED_100M(GPIOI_PIN10) | \ PIN_OSPEED_100M(GPIOI_PIN11) | \ PIN_OSPEED_100M(GPIOI_PIN12) | \ PIN_OSPEED_100M(GPIOI_PIN13) | \ PIN_OSPEED_100M(GPIOI_PIN14) | \ PIN_OSPEED_100M(GPIOI_PIN15)) #define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ PIN_PUPDR_FLOATING(GPIOI_PIN15)) #define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ PIN_ODR_HIGH(GPIOI_PIN1) | \ PIN_ODR_HIGH(GPIOI_PIN2) | \ PIN_ODR_HIGH(GPIOI_PIN3) | \ PIN_ODR_HIGH(GPIOI_PIN4) | \ PIN_ODR_HIGH(GPIOI_PIN5) | \ PIN_ODR_HIGH(GPIOI_PIN6) | \ PIN_ODR_HIGH(GPIOI_PIN7) | \ PIN_ODR_HIGH(GPIOI_PIN8) | \ PIN_ODR_HIGH(GPIOI_PIN9) | \ PIN_ODR_HIGH(GPIOI_PIN10) | \ PIN_ODR_HIGH(GPIOI_PIN11) | \ PIN_ODR_HIGH(GPIOI_PIN12) | \ PIN_ODR_HIGH(GPIOI_PIN13) | \ PIN_ODR_HIGH(GPIOI_PIN14) | \ PIN_ODR_HIGH(GPIOI_PIN15)) #define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ PIN_AFIO_AF(GPIOI_PIN1, 0) | \ PIN_AFIO_AF(GPIOI_PIN2, 0) | \ PIN_AFIO_AF(GPIOI_PIN3, 0) | \ PIN_AFIO_AF(GPIOI_PIN4, 0) | \ PIN_AFIO_AF(GPIOI_PIN5, 0) | \ PIN_AFIO_AF(GPIOI_PIN6, 0) | \ PIN_AFIO_AF(GPIOI_PIN7, 0)) #define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ PIN_AFIO_AF(GPIOI_PIN9, 0) | \ PIN_AFIO_AF(GPIOI_PIN10, 0) | \ PIN_AFIO_AF(GPIOI_PIN11, 0) | \ PIN_AFIO_AF(GPIOI_PIN12, 0) | \ PIN_AFIO_AF(GPIOI_PIN13, 0) | \ PIN_AFIO_AF(GPIOI_PIN14, 0) | \ PIN_AFIO_AF(GPIOI_PIN15, 0)) #if !defined(_FROM_ASM_) #ifdef __cplusplus extern "C" { #endif void boardInit(void); #ifdef __cplusplus } #endif #endif /* _FROM_ASM_ */ #endif /* _BOARD_H_ */

I compared the mcuconfig.h from chibios_2.x with the 3.x. I made a few changes in the mcuconfig.h from 3.x, like you se below. Do you ment that? /* ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /* * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. */ #define STM32F4xx_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 8 #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE /* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC2_DMA_PRIORITY 2 #define STM32_ADC_ADC3_DMA_PRIORITY 2 #define STM32_ADC_IRQ_PRIORITY 6 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. */ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 /* * EXT driver system settings. */ #define STM32_EXT_EXTI0_IRQ_PRIORITY 6 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15 /* * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE #define STM32_GPT_USE_TIM9 FALSE #define STM32_GPT_USE_TIM11 FALSE #define STM32_GPT_USE_TIM12 FALSE #define STM32_GPT_USE_TIM14 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 #define STM32_GPT_TIM9_IRQ_PRIORITY 7 #define STM32_GPT_TIM11_IRQ_PRIORITY 7 #define STM32_GPT_TIM12_IRQ_PRIORITY 7 #define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. */ #define HAL_USE_I2C TRUE #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 TRUE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_I2C1_DMA_ERROR_HOOK() osalSysHalt("DMA failure") #define STM32_I2C_I2C2_DMA_ERROR_HOOK() osalSysHalt("DMA failure") #define STM32_I2C_I2C3_DMA_ERROR_HOOK() osalSysHalt("DMA failure") #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM9 FALSE #define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM9_IRQ_PRIORITY 7 /* * MAC driver system settings. */ #define STM32_MAC_TRANSMIT_BUFFERS 2 #define STM32_MAC_RECEIVE_BUFFERS 4 #define STM32_MAC_BUFFERS_SIZE 1522 #define STM32_MAC_PHY_TIMEOUT 100 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE #define STM32_MAC_ETH1_IRQ_PRIORITY 13 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 /* * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 #define STM32_PWM_TIM5_IRQ_PRIORITY 7 #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #define STM32_PWM_TIM9_IRQ_PRIORITY 7 /* * SDC driver system settings. */ #define STM32_SDC_SDIO_DMA_PRIORITY 3 #define STM32_SDC_SDIO_IRQ_PRIORITY 9 #define STM32_SDC_WRITE_TIMEOUT_MS 250 #define STM32_SDC_READ_TIMEOUT_MS 25 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) /* * SERIAL driver system settings. */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 TRUE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 #define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. */ #define HAL_USE_SPI FALSE #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI4_DMA_PRIORITY 1 #define STM32_SPI_SPI5_DMA_PRIORITY 1 #define STM32_SPI_SPI6_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_SPI4_IRQ_PRIORITY 10 #define STM32_SPI_SPI5_IRQ_PRIORITY 10 #define STM32_SPI_SPI6_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 /* * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_UART4 FALSE #define STM32_UART_USE_UART5 FALSE #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_UART4_IRQ_PRIORITY 12 #define STM32_UART_UART5_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. */ #define STM32_USB_USE_OTG1 FALSE #define STM32_USB_USE_OTG2 FALSE #define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG2_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO #define STM32_USB_OTG_THREAD_STACK_SIZE 128 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 In inserted everything from the 2.x that wasn't declared in the 3.x Now I got another error regarding the USB. USB driver activated but no USB peripheral assigned In the mcuconfig.h (above) I have set "STM32_USB_USE_OTG" both on FALSE. So they are disabled. Regarding this I don't understand the USB error?

Ok, I set "STM32_PWM_USE_TIM4" on TRUE and "STM32_PWM_USE_ADVANCED" also on TRUE. After compiling it the errror still appears.

Oh I forgot, here is the whole mcuconfig.h file: /* ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /* * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. */ #define STM32F4xx_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 8 #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE /* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC2_DMA_PRIORITY 2 #define STM32_ADC_ADC3_DMA_PRIORITY 2 #define STM32_ADC_IRQ_PRIORITY 6 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. */ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 /* * EXT driver system settings. */ #define STM32_EXT_EXTI0_IRQ_PRIORITY 6 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15 /* * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE #define STM32_GPT_USE_TIM9 FALSE #define STM32_GPT_USE_TIM11 FALSE #define STM32_GPT_USE_TIM12 FALSE #define STM32_GPT_USE_TIM14 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 #define STM32_GPT_TIM9_IRQ_PRIORITY 7 #define STM32_GPT_TIM11_IRQ_PRIORITY 7 #define STM32_GPT_TIM12_IRQ_PRIORITY 7 #define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. */ #define HAL_USE_I2C TRUE #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 TRUE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM9 FALSE #define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM9_IRQ_PRIORITY 7 /* * MAC driver system settings. */ #define STM32_MAC_TRANSMIT_BUFFERS 2 #define STM32_MAC_RECEIVE_BUFFERS 4 #define STM32_MAC_BUFFERS_SIZE 1522 #define STM32_MAC_PHY_TIMEOUT 100 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE #define STM32_MAC_ETH1_IRQ_PRIORITY 13 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 /* * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED TRUE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 #define STM32_PWM_TIM5_IRQ_PRIORITY 7 #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #define STM32_PWM_TIM9_IRQ_PRIORITY 7 /* * SDC driver system settings. */ #define STM32_SDC_SDIO_DMA_PRIORITY 3 #define STM32_SDC_SDIO_IRQ_PRIORITY 9 #define STM32_SDC_WRITE_TIMEOUT_MS 250 #define STM32_SDC_READ_TIMEOUT_MS 25 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) /* * SERIAL driver system settings. */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 #define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. */ #define HAL_USE_SPI FALSE #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI4_DMA_PRIORITY 1 #define STM32_SPI_SPI5_DMA_PRIORITY 1 #define STM32_SPI_SPI6_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_SPI4_IRQ_PRIORITY 10 #define STM32_SPI_SPI5_IRQ_PRIORITY 10 #define STM32_SPI_SPI6_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 /* * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_UART4 FALSE #define STM32_UART_USE_UART5 FALSE #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_UART4_IRQ_PRIORITY 12 #define STM32_UART_UART5_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. */ #define STM32_USB_USE_OTG1 FALSE #define STM32_USB_USE_OTG2 TRUE #define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG2_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO #define STM32_USB_OTG_THREAD_STACK_SIZE 128 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0

Thanks for the quick answer. I couldn't found "PWMD4" in the mcuconfig.h file. But I found this /* * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED TRUE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 #define STM32_PWM_TIM5_IRQ_PRIORITY 7 #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #define STM32_PWM_TIM9_IRQ_PRIORITY 7 I changed "#define STM32_PWM_USE_ADVANCED FALSE" to "#define STM32_PWM_USE_ADVANCED TRUE", like you see above. But I still get these errors from before? Do I have to enable some of the timers too? Or is there anything else I have to change?

Ok. I began a complete new Project and followed the ugfx tutorial for ChibiStudio, just that I did everything with ChibiOS Version 3. But I ran into a few problems. The first one was the error: error: #error "SPI5 not present in the selected device" I first thought that it has something to do with the device. I use a Embest Base Board with an STM32F407VG Microcontroller. When I followed the Tutorial I included the files "/ugfx/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x". But the included Makefile had as option "CHIBIOS_LDSCRIPT = STM32F429xI.ld". So I thought that I have to change that into "CHIBIOS_LDSCRIPT = STM32F407xG.ld" is that right? But the error was still there. After changing the mcuconf.h from #define HAL_USE_SPI TRUE #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 TRUE #define STM32_SPI_USE_SPI6 FALSE to (everything FALSE) #define HAL_USE_SPI FALSE #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE The Error didn't appear anymore! But I don't know, if thats right? When I compile again (with every SPI Option = FALSE) some other Errors appeared regardin the "board_SSD2119 file". Here is the Output. 20:04:27 **** Incremental Build of configuration Default for project PowerSupplyChibiOs3 **** make -j4 all . C Compiler Options.... Compiling board.c Compiling ../../ugfx/src/gfx.c arm-none-eabi-gcc -c -ggdb -O0 -mcpu=cortex-m4 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -fomit-frame-pointer -Wall -Wextra -Wstrict-prototypes -fverbose-asm -MMD -MP -MF .build/dep/fakethumbfile.o.d -I. -I../../ugfx -I../../ugfx/3rdparty/tinygl-0.4-ugfx/include -I../../ugfx/boards/base/Embest-STM32-DMSTF4BB -I../../ugfx/drivers/gdisp/SSD2119 -I../../ugfx/demos/modules/gdisp/basics -I../../chibios30/os/common/ports/ARMCMx/devices/STM32F4xx -I../../chibios30/os/ext/CMSIS/include -I../../chibios30/os/ext/CMSIS/ST -I../../chibios30/os/rt/include -I../../chibios30/os/rt/ports/ARMCMx -I../../chibios30/os/rt/ports/ARMCMx/compilers/GCC -I../../chibios30/os/hal/osal/rt -I../../chibios30/os/hal/include -I../../chibios30/os/hal/ports/common/ARMCMx -I../../chibios30/os/hal/ports/STM32/STM32F4xx -I../../chibios30/os/hal/ports/STM32/LLD -I../../chibios30/os/hal/ports/STM32/LLD/DACv1 -I../../chibios30/os/hal/ports/STM32/LLD/GPIOv2 -I../../chibios30/os/hal/ports/STM32/LLD/I2Cv1 -I../../chibios30/os/hal/ports/STM32/LLD/OTGv1 -I../../chibios30/os/hal/ports/STM32/LLD/RTCv2 -I../../chibios30/os/hal/ports/STM32/LLD/SPIv1 -I../../chibios30/os/hal/ports/STM32/LLD/TIMv1 -I../../chibios30/os/hal/ports/STM32/LLD/USARTv1 -I../../chibios30/os/hal/ports/STM32/LLD/FSMCv1 -DGFX_USE_CHIBIOS=TRUE -DGFX_USE_OS_CHIBIOS=TRUE -DCORTEX_USE_FPU=TRUE -DUSE_FPU=hard -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -mthumb -DTHUMB fakethumbfile.c -o .build/obj/fakethumbfile.o . Compiling ../../ugfx/src/gos/gos_chibios.c Assembler Options..... In file included from ../../ugfx/src/../gfx.h:185:0, from ../../ugfx/src/gfx.c:16: ../../ugfx/src/../src/gdisp/gdisp_rules.h:65:6: warning: #warning "GDISP: GDISP_NEED_ANTIALIAS has been set but your hardware does not support reading back pixels. Anti-aliasing will only occur for filled characters." [-Wcpp] #warning "GDISP: GDISP_NEED_ANTIALIAS has been set but your hardware does not support reading back pixels. Anti-aliasing will only occur for filled characters." ^ In file included from ../../ugfx/src/../gfx.h:189:0, from ../../ugfx/src/gfx.c:16: ../../ugfx/src/../src/gtimer/gtimer_rules.h:22:5: warning: #warning "GTIMER: GDISP_NEED_MULTITHREAD has not been specified." [-Wcpp] #warning "GTIMER: GDISP_NEED_MULTITHREAD has not been specified." ^ ../../ugfx/src/../src/gtimer/gtimer_rules.h:23:5: warning: #warning "GTIMER: Make sure you are not performing any GDISP/GWIN drawing operations in the timer callback!" [-Wcpp] #warning "GTIMER: Make sure you are not performing any GDISP/GWIN drawing operations in the timer callback!" ^ arm-none-eabi-gcc -c -ggdb -O0 -mcpu=cortex-m4 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -fomit-frame-pointer -Wall -Wextra -Wstrict-prototypes -fverbose-asm -MMD -MP -MF .build/dep/fakethumbfile.o.d -I. -I../../ugfx -I../../ugfx/3rdparty/tinygl-0.4-ugfx/include -I../../ugfx/boards/base/Embest-STM32-DMSTF4BB -I../../ugfx/drivers/gdisp/SSD2119 -I../../ugfx/demos/modules/gdisp/basics -I../../chibios30/os/common/ports/ARMCMx/devices/STM32F4xx -I../../chibios30/os/ext/CMSIS/include -I../../chibios30/os/ext/CMSIS/ST -I../../chibios30/os/rt/include -I../../chibios30/os/rt/ports/ARMCMx -I../../chibios30/os/rt/ports/ARMCMx/compilers/GCC -I../../chibios30/os/hal/osal/rt -I../../chibios30/os/hal/include -I../../chibios30/os/hal/ports/common/ARMCMx -I../../chibios30/os/hal/ports/STM32/STM32F4xx -I../../chibios30/os/hal/ports/STM32/LLD -I../../chibios30/os/hal/ports/STM32/LLD/DACv1 -I../../chibios30/os/hal/ports/STM32/LLD/GPIOv2 -I../../chibios30/os/hal/ports/STM32/LLD/I2Cv1 -I../../chibios30/os/hal/ports/STM32/LLD/OTGv1 -I../../chibios30/os/hal/ports/STM32/LLD/RTCv2 -I../../chibios30/os/hal/ports/STM32/LLD/SPIv1 -I../../chibios30/os/hal/ports/STM32/LLD/TIMv1 -I../../chibios30/os/hal/ports/STM32/LLD/USARTv1 -I../../chibios30/os/hal/ports/STM32/LLD/FSMCv1 -DGFX_USE_CHIBIOS=TRUE -DGFX_USE_OS_CHIBIOS=TRUE -DCORTEX_USE_FPU=TRUE -DUSE_FPU=hard -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -mthumb -DTHUMB fakethumbfile.s -o .build/obj/fakethumbfile.o . Linker Options........ arm-none-eabi-gcc -Wl,--defsym=__process_stack_size__=0x400 -Wl,--defsym=__main_stack_size__=0x400 -mcpu=cortex-m4 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -nostartfiles -mthumb -T../../chibios30/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld -L../../chibios30/os/common/ports/ARMCMx/compilers/GCC -lm .build/obj/fakethumbfile.o -o .build/PowerSupplyChibiOs3.elf . Compiling ../../ugfx/src/gos/gos_freertos.c Compiling ../../ugfx/src/gos/gos_win32.c Compiling ../../ugfx/src/gos/gos_linux.c Compiling ../../ugfx/src/gos/gos_osx.c Compiling ../../ugfx/src/gos/gos_raw32.c Compiling ../../ugfx/src/gos/gos_ecos.c Compiling ../../ugfx/src/gos/gos_rawrtos.c Compiling ../../ugfx/src/gos/gos_arduino.c Compiling ../../ugfx/src/gos/gos_cmsis.c Compiling ../../ugfx/src/gos/gos_nios.c Compiling ../../ugfx/src/gos/gos_x_threads.c Compiling ../../ugfx/src/gos/gos_x_heap.c Compiling ../../ugfx/src/gdriver/gdriver.c Compiling ../../ugfx/src/gqueue/gqueue.c Compiling ../../ugfx/src/gdisp/gdisp.c Compiling ../../ugfx/src/gdisp/gdisp_fonts.c Compiling ../../ugfx/src/gdisp/gdisp_pixmap.c Compiling ../../ugfx/src/gdisp/gdisp_image.c Compiling ../../ugfx/src/gdisp/gdisp_image_native.c Compiling ../../ugfx/src/gdisp/gdisp_image_gif.c Compiling ../../ugfx/src/gdisp/gdisp_image_bmp.c Compiling ../../ugfx/src/gdisp/gdisp_image_jpg.c Compiling ../../ugfx/src/gdisp/gdisp_image_png.c Compiling ../../ugfx/src/gdisp/mcufont/mf_encoding.c Compiling ../../ugfx/src/gdisp/mcufont/mf_font.c Compiling ../../ugfx/src/gdisp/mcufont/mf_justify.c Compiling ../../ugfx/src/gdisp/mcufont/mf_kerning.c Compiling ../../ugfx/src/gdisp/mcufont/mf_rlefont.c Compiling ../../ugfx/src/gdisp/mcufont/mf_bwfont.c Compiling ../../ugfx/src/gdisp/mcufont/mf_scaledfont.c Compiling ../../ugfx/src/gdisp/mcufont/mf_wordwrap.c Compiling ../../ugfx/src/gevent/gevent.c Compiling ../../ugfx/src/gtimer/gtimer.c Compiling ../../ugfx/src/gwin/gwin.c Compiling ../../ugfx/src/gwin/gwin_widget.c Compiling ../../ugfx/src/gwin/gwin_wm.c Compiling ../../ugfx/src/gwin/gwin_console.c Compiling ../../ugfx/src/gwin/gwin_graph.c Compiling ../../ugfx/src/gwin/gwin_button.c Compiling ../../ugfx/src/gwin/gwin_slider.c Compiling ../../ugfx/src/gwin/gwin_checkbox.c Compiling ../../ugfx/src/gwin/gwin_image.c Compiling ../../ugfx/src/gwin/gwin_label.c Compiling ../../ugfx/src/gwin/gwin_radio.c Compiling ../../ugfx/src/gwin/gwin_list.c Compiling ../../ugfx/src/gwin/gwin_progressbar.c Compiling ../../ugfx/src/gwin/gwin_container.c Compiling ../../ugfx/src/gwin/gwin_frame.c Compiling ../../ugfx/src/gwin/gwin_tabset.c Compiling ../../ugfx/src/gwin/gwin_gl3d.c Compiling ../../ugfx/src/gwin/gwin_keyboard.c Compiling ../../ugfx/src/gwin/gwin_keyboard_layout.c Compiling ../../ugfx/src/gwin/gwin_textedit.c Compiling ../../ugfx/src/ginput/ginput.c Compiling ../../ugfx/src/ginput/ginput_mouse.c Compiling ../../ugfx/src/ginput/ginput_keyboard.c Compiling ../../ugfx/src/ginput/ginput_keyboard_microcode.c Compiling ../../ugfx/src/ginput/ginput_toggle.c Compiling ../../ugfx/src/ginput/ginput_dial.c Compiling ../../ugfx/src/gadc/gadc.c Compiling ../../ugfx/src/gaudio/gaudio.c Compiling ../../ugfx/src/gmisc/gmisc.c Compiling ../../ugfx/src/gmisc/gmisc_arrayops.c Compiling ../../ugfx/src/gmisc/gmisc_matrix2d.c Compiling ../../ugfx/src/gmisc/gmisc_trig.c Compiling ../../ugfx/src/gmisc/gmisc_hittest.c Compiling ../../ugfx/src/gfile/gfile.c Compiling ../../ugfx/src/gfile/gfile_fs_native.c Compiling ../../ugfx/src/gfile/gfile_fs_ram.c Compiling ../../ugfx/src/gfile/gfile_fs_rom.c Compiling ../../ugfx/src/gfile/gfile_fs_fatfs.c Compiling ../../ugfx/src/gfile/gfile_fs_petitfs.c Compiling ../../ugfx/src/gfile/gfile_fs_mem.c Compiling ../../ugfx/src/gfile/gfile_fs_chibios.c Compiling ../../ugfx/src/gfile/gfile_fs_strings.c Compiling ../../ugfx/src/gfile/gfile_printg.c Compiling ../../ugfx/src/gfile/gfile_scang.c Compiling ../../ugfx/src/gfile/gfile_stdio.c Compiling ../../ugfx/src/gfile/gfile_fatfs_wrapper.c Compiling ../../ugfx/src/gfile/gfile_fatfs_diskio_chibios.c Compiling ../../ugfx/src/gfile/gfile_petitfs_wrapper.c Compiling ../../ugfx/src/gfile/gfile_petitfs_diskio_chibios.c Compiling ../../ugfx/src/gtrans/gtrans.c Compiling ../../ugfx/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c Compiling ../../ugfx/drivers/ginput/touch/STMPE811/gmouse_lld_STMPE811.c Compiling ../../ugfx/demos/modules/gdisp/basics/main.c Compiling ../../chibios30/os/common/ports/ARMCMx/compilers/GCC/vectors.c In file included from ../../ugfx/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c:16:0: ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:31:14: error: unknown type name 'PWMConfig' static const PWMConfig pwmcfg = { ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:33:2: warning: excess elements in scalar initializer 100, /* PWM period is 100 cycles. */ ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:33:2: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:34:2: warning: excess elements in scalar initializer 0, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:34:2: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:35:2: warning: braces around scalar initializer { ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:35:2: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:36:3: warning: braces around scalar initializer {PWM_OUTPUT_ACTIVE_HIGH, 0}, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:36:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:36:4: error: 'PWM_OUTPUT_ACTIVE_HIGH' undeclared here (not in a function) {PWM_OUTPUT_ACTIVE_HIGH, 0}, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:36:3: warning: excess elements in scalar initializer {PWM_OUTPUT_ACTIVE_HIGH, 0}, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:36:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: braces around scalar initializer {PWM_OUTPUT_ACTIVE_HIGH, 0}, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:37:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: braces around scalar initializer {PWM_OUTPUT_ACTIVE_HIGH, 0}, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:38:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: braces around scalar initializer {PWM_OUTPUT_ACTIVE_HIGH, 0} ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: excess elements in scalar initializer ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:39:3: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:40:2: warning: excess elements in scalar initializer }, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:40:2: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:41:2: warning: excess elements in scalar initializer 0, ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:41:2: warning: (near initialization for 'pwmcfg') ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:43:1: warning: excess elements in scalar initializer }; ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:43:1: warning: (near initialization for 'pwmcfg') In file included from ../../ugfx/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c:16:0: ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h: In function 'init_board': ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:78:1: warning: multi-line comment [-Wcomment] // FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:91:3: warning: implicit declaration of function 'pwmStart' [-Wimplicit-function-declaration] pwmStart(&PWMD4, &pwmcfg); ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:91:13: error: 'PWMD4' undeclared (first use in this function) pwmStart(&PWMD4, &pwmcfg); ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:91:13: note: each undeclared identifier is reported only once for each function it appears in ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:93:3: warning: implicit declaration of function 'pwmEnableChannel' [-Wimplicit-function-declaration] pwmEnableChannel(&PWMD4, 1, 100); ^ ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h: In function 'set_backlight': ../../ugfx/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h:113:20: error: 'PWMD4' undeclared (first use in this function) pwmEnableChannel(&PWMD4, 1, percent); ^ make: *** [.build/obj/GFXLIB/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.o] Error 1 make: *** Waiting for unfinished jobs.... Can someone help me with this Problems.

Thanks, I asked in the ChibiOS Forum. They told me that the ChibiOS repository that i used (it is the one from the ugfx tutorial for Chibistudio) is very old and so the .ld file is. I downloaded the newest version but now I have problems with including it to the ugfx makefile, because the file structure is very different from the release from the tutorial. Had someone ever problems with it? How can i integrate the new ChibiOS release into the ugfx Project? They couldn't help me with this issue in the ChibiOS Forum. I added the newest release below. ChibiOS_17.6.0.zip

Looks the ChibiOS linker file like that? /* ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /* * ST32F407xG memory setup. */ __main_stack_size__ = 0x0400; __process_stack_size__ = 0x0400; MEMORY { flash : org = 0x08000000, len = 1M ram : org = 0x20000000, len = 112k ethram : org = 0x2001C000, len = 16k ccmram : org = 0x10000000, len = 64k } __ram_start__ = ORIGIN(ram); __ram_size__ = LENGTH(ram); __ram_end__ = __ram_start__ + __ram_size__; ENTRY(ResetHandler) SECTIONS { . = 0; _text = .; startup : ALIGN(16) SUBALIGN(16) { KEEP(*(vectors)) } > flash constructors : ALIGN(4) SUBALIGN(4) { PROVIDE(__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE(__init_array_end = .); } > flash destructors : ALIGN(4) SUBALIGN(4) { PROVIDE(__fini_array_start = .); KEEP(*(.fini_array)) KEEP(*(SORT(.fini_array.*))) PROVIDE(__fini_array_end = .); } > flash .text : ALIGN(16) SUBALIGN(16) { *(.text.startup.*) *(.text) *(.text.*) *(.rodata) *(.rodata.*) *(.glue_7t) *(.glue_7) *(.gcc*) } > flash .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > flash .ARM.exidx : { PROVIDE(__exidx_start = .); *(.ARM.exidx* .gnu.linkonce.armexidx.*) PROVIDE(__exidx_end = .); } > flash .eh_frame_hdr : { *(.eh_frame_hdr) } > flash .eh_frame : ONLY_IF_RO { *(.eh_frame) } > flash .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash . = ALIGN(4); _etext = .; _textdata = _etext; .stacks : { . = ALIGN(8); __main_stack_base__ = .; . += __main_stack_size__; . = ALIGN(8); __main_stack_end__ = .; __process_stack_base__ = .; __main_thread_stack_base__ = .; . += __process_stack_size__; . = ALIGN(8); __process_stack_end__ = .; __main_thread_stack_end__ = .; } > ram .data ALIGN(4) : ALIGN(4) { . = ALIGN(4); PROVIDE(_data = .); *(.data) *(.data.*) *(.ramtext) . = ALIGN(4); PROVIDE(_edata = .); } > ram AT > flash .bss ALIGN(4) : ALIGN(4) { . = ALIGN(4); PROVIDE(_bss_start = .); *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); PROVIDE(_bss_end = .); } > ram } PROVIDE(end = .); _end = .; __heap_base__ = _end; __heap_end__ = __ram_end__; Where do I have to set the interrupt stack?

Thanks. The unmodified demo also does not work. The display stays empty. I tried it now.

Hey I have got a Problem I started a Project: Hardware: STM32F407VG with Embest Base Board (Controller: SSD2119 and STMPE811) OS: ChibiOS 2.0 The first step was that i tried to implement an image and text. That worked fine. After that i tried to implement a button. So I used parts of the demo /gwin/button. It compiles without any error. But the screen still is empty when i load it to the STM Board. I debugged it step by step and I saw that it alwas stops after execution one line. I enabled some debug options in chconf.h and then the Debugger always stops at the end of following if-statement: #if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) /** * @brief Public trace buffer. */ ch_trace_buffer_t dbg_trace_buffer; /** * @brief Trace circular buffer subsystem initialization. * @note Internal use only. */ void _trace_init(void) { dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE; dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; } /** * @brief Inserts in the circular debug trace buffer a context switch record. * * @param[in] otp the thread being switched out * * @notapi */ void dbg_trace(Thread *otp) { dbg_trace_buffer.tb_ptr->se_time = chTimeNow(); dbg_trace_buffer.tb_ptr->se_tp = currp; dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; if (++dbg_trace_buffer.tb_ptr >= &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE]) dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; } #endif /* CH_DBG_ENABLE_TRACE */ So i read in the documentation that it should have something to do with a stack size problem. I tried to increase the main stack size and process stack size from 0x0400 to 0x0F00, but this didn't solve my problem How can I find out which stack or thread has an overflow? Thank you in advance.